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US 9,001,548 B2Granted
Memory device interface methods, apparatus, and systems
AssigneeMicron Technology, Inc.
InventorJoe M. Jeddeloh
Life of this patent
Estimating the term…
Abstract
Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and to couple to a plurality of stacked memory arrays using a data bus and a maintenance bus, wherein the data bus is separate from the maintenance bus, the plurality of stacked memory arrays forming two or more memory chips, the memory controller configured to control access to memory locations within the plurality of stacked memory arrays.
Claims20
An interface chip comprising:
- a memory controller configured to couple to a processor and to couple to a plurality of stacked memory arrays using a data bus and a maintenance bus, wherein the data bus is separate from the maintenance bus, the plurality of stacked memory arrays forming two or more memory chips, the memory controller configured to control access to memory locations within the plurality of stacked memory arrays.
A memory system comprising:
- a memory die stack including:
- a first memory die and a second memory die, at least one of the first memory die or the second memory die including a plurality of vias;
- and
- a plurality of through wafer interconnects (TWIs) extending through the plurality of vias;
- and
- an interface chip including a memory controller coupled to the plurality of TWIs, the memory controller configured to control access to memory locations within memory die stack.
3 more elements
A system comprising:
- a processor;
- a plurality of memory banks, wherein one or more memory banks of the plurality of memory banks includes a plurality of dynamic random access memory (DRAM) arrays, and wherein each memory bank includes a plurality of independent interconnects;
- and
- an interface chip configured to interconnect the plurality of memory banks with the processor, the interface chip including a DRAM controller coupled to at least a portion of the plurality of independent interconnects, the DRAM controller configured to control access to memory locations within the plurality of memory banks.
1 more element
Dependencies are inferred from the claim text.