3D structure for advanced SRAM design to avoid half-selected issue

A static random access memory (SRAM) device comprising:

• a plurality of memory array layers vertically disposed one above another, each memory array layer comprising a plurality of memory cells and a word line disposed thereon, wherein each word line is connected to the plurality of the memory cells disposed on its memory array layer, wherein the number of memory cells in a layer corresponds to a predetermined memory page size;
• a layer decoder circuit on each memory array layer, each layer decoder circuit being configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer;
• a word line driver configured to drive the word line disposed on the selected memory array layer;
• and
• a plurality of complementary bit line pairs, each complementary bit line pair extending vertically to couple to a memory cell in each memory array layer;
• wherein the SRAM device is configured to activate only the word line connected to those memory cells selected by the SRAM address so that a read operation or a write operation does not result in a non-selected memory cell consuming unnecessary power.

A method in a static random access memory (SRAM) device comprising:

• providing a plurality of memory array layers vertically disposed one above another, each memory array layer comprising a plurality of memory cells disposed thereon, each memory array layer further comprising a layer decoder configured to decode a portion of an SRAM address to determine the memory array layer on which the memory cells addressed by the SRAM address are disposed;
• providing a word line on each memory array layer, wherein each word line is connected to each memory cell in the memory array layer on which the word line is disposed;
• and
• providing a plurality of complementary bit line pairs, each complementary bit line pair extending vertically to couple to a memory cell in each memory array layer;
• wherein each word line is connected to a number of memory cells equal to the number of input/output data lines in the device.