NOR-based BCAM/TCAM cell and array with NAND scalability

A sector of M×N 2T-string NOR-based CAM logic cell array comprising:

• a M×N matrix of 2T-string NOR-based CAM logic cells including M paired horizontal word lines coupled through N vertical pages, M and N being properly selected integer numbers, each paired horizontal word lines including a first word line and a second word line, each of the N vertical pages including M 2T-string NOR-based CAM logic cells connected in parallel sharing a vertical local bit line and a vertical local source line, the vertical local source line being accessed by a horizontal global source line via a first select transistor commonly for the N vertical pages and the vertical local bit line being accessed by a vertical global bit line via a second select transistor individually for each of the N vertical page, each of the M 2T-string NOR-based CAM logic cells comprising:
• a first NAND flash transistor connected a second NAND flash transistor in series, the first NAND flash transistor including a first gate coupled to the first word line and a drain node coupled to the vertical local bit line, the second NAND flash transistor including a second gate coupled to the second word line and a source node coupled to the vertical local source line, each of the first NAND flash transistor and the second NAND flash transistor being associated with at least a first threshold voltage level Vt0 of a negative value corresponding to a first physical state or a second threshold voltage level Vt1 of a positive value corresponding to a second physical state, wherein the first NAND flash transistor and the second NAND flash transistor being respectively associated with the first physical state and the second physical state define a first CAM logic state “0” and the first NAND flash transistor and the second NAND flash transistor being respectively associated with the second physical state and the first physical state define a second CAM logic state “1”;
• a search word device configured to generate at least M-bit logic outputs, the M pairs of outputs being respectively coupled to the M paired horizontal word lines, each pair of outputs being either at a ground voltage VSS=0V or at a complementary power voltage VDD level for initiating a compare operation to determine if a single logic-bit match is found for each of the M 2T-string NOR-based CAM logic cells at any one of the first CAM logic state “0” and the second CAM logic state “1” when one of the first NAND flash transistor and the second NAND flash transistor is in non-conduction state;
• a priority decoder device configured to receive N vertical global bit lines respectively associated with the N vertical pages as N match lines for sending a match information to a hit line if at least one M-logic-bit match is found for one vertical page with all the M 2T-string NOR-based CAM logic cells respectively at either one of the first CAM logic state “0” or the second CAM logic state “1” and generating a priority list if multiple matches are found respectively for corresponding multiple vertical pages;
• and
• a Comparand address generator device coupled to the N match lines and received the match information from the N match lines and the hit line to generate an address list associated with one or more vertical pages having the at least one M-logic-bit match or one or more partial matches depending on the priority list.