Common element pixel architecture (CEPA) for fast speed readout
AssigneeSemiconductor Components Industries, LLC
InventorXiangli Li
Life of this patent
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Abstract
The present invention relates to a common element pixel architecture (CEPA) imager. The CEPA includes a first column of pixels and a second column of pixels. The CEPA also includes a first column line and a second column line. A first group of pixels is arranged including pixels from the first column and the second column coupled to the first column line. A second group of pixels is arranged including other pixels from the first column and the second column coupled to the second column line.
Claims11
A common element pixel architecture (CEPA) imager comprising:
- a first column of pixels;
- a second column of pixels;
- a first column line;
- a second column line;
- a first group of pixels including pixels from the first column and the second column coupled to the first column line;
- a second group of pixels including other pixels from the first column and the second column coupled to the second column line;
- a color filter array having a color pattern arranged on both the first group of pixels and the second group of pixels;
- a controller configured to simultaneously output pixel values from pixels of a first color in the first column and in the first group over the first column line and from pixels of the first color in the first column and in the second group over the second column line;
- a first readout circuit coupling the pixels in the first group of pixels to the first column line;
- and
- a second readout circuit coupling the pixels in the second group of pixels to the second column line, wherein the first readout circuit and the second readout circuit respectively include a source follower transistor including a drain terminal coupled to a reference voltage line and a reset transistor including a drain terminal coupled to the reference voltage line.
A common element pixel architecture (CEPA) imager comprising:
- a first column of pixels and a second column of pixels, each of the pixels including a photodiode and a transfer transistor, wherein the transfer transistor of each pixel in the first column of pixels is controlled by a respective transfer line and wherein each transfer line is coupled exclusively to pixels in a common row;
- a first column line;
- a second column line;
- a first group of pixels including pixels from the first column and the second column;
- a second group of pixels including other pixels from the first column and the second column;
- a first readout circuit coupling each of the transfer transistors in the first group of pixels to the first column line;
- and
- a second readout circuit coupling each of the transfer transistors in the second group of pixels to the second column line, wherein the first readout circuit and the second readout circuit respectively include a source follower transistor including a drain terminal coupled to a reference voltage line and a reset transistor including a drain terminal coupled to the reference voltage line.
Dependencies are inferred from the claim text.