Frame timing synchronization for an inline scaler using multiple buffer thresholds
AssigneeApple Inc.
InventorVijay G. Prabakaran
Life of this patent
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AssigneeApple Inc.
InventorVijay G. Prabakaran
Estimating the term…
During downscaling of an image, a scaler may generate a specified number ‘M’ output lines of an output frame for each specified number ‘N’ input lines of an input frame, and store the output lines in a buffer. The scaler may keep the output horizontal line durations consistent throughout the active line period, with a horizontal line duration ratio of M/N between input and output frame streams. ‘M’ threshold values may be stored in a lookup table, and for each output line the relative position of the output line within the output frame may be used to look up a corresponding threshold value in the lookup table, and the timing generator may wait until the buffer occupancy reaches the corresponding threshold value before outputting the output line from the buffer. To guarantee even line widths, the threshold values may be assigned values that depend on the scaling ratio used.
A frame timing controller comprising:
A graphics system comprising:
A method for timing scaled image frames, the method comprising:
Dependencies are inferred from the claim text.