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US 9,001,138 B2Granted
2-D gather instruction and a 2-D cache
AssigneeIntel Corporation
InventorsBoris Ginzburg, Oleg Margulis
Life of this patent
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Abstract
A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image.
Claims23
A processor comprising:
- a pre-fetch unit to fetch one or more instructions,
- a decode unit to decode the one or more instructions, wherein the one or more instructions include a two-dimensional (2-D) gather instruction,
- an execution unit to perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor, and
- a two-dimensional (2-D) cache to store the one or more sub-blocks of data in multiple cache lines, to support access to more than one cache line in a single processing cycle, to preserve a two-dimensional structure of the 2-D image, and to support mapping of the one or more sub-blocks to avoid read conflict after loading the one or more sub-blocks, wherein the 2-D cache includes
- a plurality of sets and a plurality of ways, and
- an access logic to map the one or more sub-blocks on to the plurality of sets and the plurality of ways and to perform a 2-D cache lookup, wherein the cache look-up includes
- identifying a memory block within the 2-D cache using the set and the way of the 2-D cache,
- retrieving content of a tag field within the memory block, and
- determining if a data stored in the memory block is evicted.
6 more elements
A method in a processor comprising:
- pre-fetching one or more instructions,
- decoding the one or more instructions, wherein the one or more instructions include a two-dimensional (2-D) gather instruction,
- performing the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor,
- storing the one or more sub-blocks of data in multiple cache lines of a 2-D cache, wherein the 2-D cache includes a plurality of sets and a plurality of ways,
- supporting access to more than one cache line in a single processing cycle while preserving a two-dimensional structure of the 2-D image in the 2-D cache,
- mapping the one or more sub-blocks in the 2-D cache to avoid read conflict after loading the one or more sub-blocks, wherein the mapping includes mapping the one or more sub-blocks on to the plurality of sets and the plurality of ways of the 2-D cache, and
- determining a set of the plurality of sets on to which a first coordinate of an image pixel of the one or more sub-blocks are mapped, wherein the set is determined using a result of a modulo operation performed on the first coordinate of the 2-D image and a total number of sets available in the 2-D cache.
4 more elements
A system comprising,
- a memory,
- a machine readable storage medium,
- a logic,
- a plurality of input-output devices, and
- a processor comprising a plurality of cores and a plurality of caches, wherein the plurality of caches includes a two-dimensional (2-D) cache, wherein the 2-D cache includes a plurality of sets and a plurality of way, and wherein the processor is to,
- fetch one or more instructions,
- decode the one or more instructions, wherein the one or more instructions include a two-dimensional (2-D) gather instruction,
- perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor,
- store the one or more sub-blocks of data in multiple cache lines of the 2-D cache;
- support access to more than one cache line of the 2-D cache in a single processing cycle while preserving a two-dimensional structure of the 2-D image,
- support mapping of the one or more sub-blocks, in the 2-D cache, on to the plurality of sets and the plurality of ways of the 2-D cache to avoid read conflict after loading the one or more sub-blocks, and
- determine a way of the plurality of ways on to which a second coordinate of the image pixel within the one or more sub-blocks are mapped, wherein the way is determined using a result of a modulo operation performed on the second coordinate of the 2-D image and a total number of ways available in the 2-D cache.
9 more elements
Dependencies are inferred from the claim text.