Voltage summing buffer, digital-to-analog converter and source driver of display device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorKi-Duk Kim
Life of this patent
Estimating the term…
Abstract
A digital-to-analog converter includes a first decoder, a second decoder and a voltage summing buffer. The first decoder receives upper bits of a digital signal and upper reference voltages to output an upper voltage corresponding to the upper bits. The second decoder configured to receive lower bits of the digital signal and lower reference voltages to output a lower differential voltage corresponding to the lower bits. The voltage summing buffer generates an output voltage based on the upper voltage and the lower differential voltage, such that the output voltage corresponds to the digital signal including the upper bits and the lower bits.
Claims20
A digital-to-analog converter, comprising:
- a first decoder configured to receive upper bits of a digital signal and upper reference voltages to output an upper voltage corresponding to the upper bits;
- a second decoder configured to receive lower bits of the digital signal and lower reference voltages to output a lower differential voltage corresponding to the lower bits;
- and
- a voltage summing buffer configured to generate an output voltage based on the upper voltage and the lower differential voltage, the output voltage corresponding to the digital signal including the upper bits and the lower bits.
A voltage summing buffer, comprising:
- a first differential amplifier configured to receive an output voltage and a single-ended input voltage as a first differential input to generate a first differential current to a summing node pair;
- a second differential amplifier configured to receive first and second voltages of a first differential input voltage as a second differential input to generate a second differential current to the summing node pair;
- and
- an output buffer configured to generate the output voltage based on a voltage or a current at one of the summing node pair.
A source driver of a display device, the source driver comprising:
- a reference voltage generator configured to generate upper reference voltages and lower reference voltages;
- and
- a plurality of digital-to analog converters configured to convert a plurality of digital signals to a plurality of output voltages, respectively, wherein each digital-to analog converter includes:
- a first decoder configured to receive upper bits of each digital signal and the upper reference voltages to output an upper voltage corresponding to the upper bits;
- a second decoder configured to receive lower bits of each digital signal and the lower reference voltages to output a lower differential voltage corresponding to the lower bits;
- and
- a voltage summing buffer configured to generate each output voltage of the plurality of output voltages based on the upper voltage and the lower differential voltage, each output voltage of the plurality of output voltages corresponding to one of the digital signals of the plurality of digital signals including the upper bits and the lower bits.
Dependencies are inferred from the claim text.