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US 9,000,968 B1Granted
Analog-to-digital converter with clock halting circuit
AssigneeFreescale Semiconductor, Inc.
InventorsSunny Gupta, Kumar Abhishek, Nitin Pant
Life of this patent
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Abstract
An analog to digital converter (ADC) includes a clock-halting circuit that is enabled by an externally generated trigger signal. The clock-halting circuit halts an input clock signal to the ADC for a predetermined time period and resumes the input clock signal to the ADC when the predetermined time period ends.
Claims14
A system for converting an analog signal into a digital signal, comprising:
- an analog-to-digital converter (ADC) having an input terminal for receiving the analog signal, a clock input terminal for receiving an input clock signal, and an output terminal for outputting the digital signal;
- and
- a clock-halting circuit, connected to the clock input terminal of the ADC, for halting the input clock signal to the ADC based on an external trigger signal, wherein the trigger signal toggles between logic high and low states, and wherein the clock-halting circuit includes:
- a synchronizer having an input terminal for receiving the trigger signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting a synchronous trigger signal;
- a counter circuit having an input terminal connected to the output terminal of the synchronizer for receiving the synchronous trigger signal and a clock input terminal for receiving the input clock signal, wherein the counter circuit starts a count of a predetermined set of count values after the trigger signal toggles between the logic high and low states, and wherein the predetermined set of count values corresponds to a predetermined time period;
- and
- a clock-halting latch, connected between the counter circuit and the clock input terminal of the ADC, for halting the input clock signal to the ADC for the predetermined time period.
4 more elements
An integrated circuit, comprising:
- a switched-mode power supply (SMPS), for receiving an external unregulated supply voltage and generating a regulated voltage, wherein the SMPS includes:
- a control circuit for generating a trigger signal to control switching of a switching element;
- an analog-to-digital converter (ADC) having an input terminal for receiving an analog signal, a clock input terminal for receiving an input clock signal, and an output terminal for outputting a digital signal;
- and
- a clock-halting circuit, connected between the ADC and the SMPS, for receiving the trigger signal and halting the input clock signal to the ADC, wherein the clock-halting circuit includes:
- a synchronizer having an input terminal connected to the control circuit for receiving the trigger signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting a synchronous trigger signal;
- a counter circuit having an input terminal connected to the output terminal of the synchronizer for receiving the synchronous trigger signal and a clock input terminal for receiving the input clock signal, wherein the counter circuit, when triggered by the synchronous trigger signal, starts a count of a predetermined set of count values, wherein the predetermined set of count values corresponds to a predetermined time period;
- and
- a clock-halting latch, connected to the counter circuit and the clock input terminal of the ADC, for halting the input clock signal for the predetermined time period.
6 more elements
Dependencies are inferred from the claim text.