Circuit and method for skew correction
AssigneesSTMicroelectronics S.r.l., STMicroelectronics International N.V.
InventorsPratap Narayan Singh, Stéphane Le Tual
Life of this patent
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Abstract
The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.
Claims19
A circuit comprising:
- a first transistor having first and second conduction nodes, a control node configured to receive a first timing signal for causing the first transistor to transition between conducting and non-conducting states, and a bulk node;
- a biasing circuit coupled to said bulk node of said first transistor;
- and
- a control circuit configured to
- receive at least one feedback signal during application of at least one initial control voltage to said bulk node, and
- control said biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the transition, the controlling being based on the at least one feedback signal.
A method of modifying timing of at least one of a plurality of transitions between conducting and non-conducting states of a first transistor having first and second conduction nodes, a control node, and a bulk node, the method comprising:
- applying to the control node of said first transistor a first timing signal for causing the first transistor to transition between the conducting and non-conducting states;
- and
- controlling, by a control circuit, a biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the at least one of said plurality of transitions of the first transistor, the controlling being based upon at least one feedback signal received by the control circuit during application of at least one initial control voltage to said bulk node.
A circuit comprising:
- a first transistor having first and second conduction nodes, a control node configured to receive a first timing signal for causing the first transistor to transition between conducting and non-conducting states, and a bulk node;
- a biasing circuit coupled to the bulk node of said first transistor;
- a second transistor having first and second conduction nodes, a control node configured to receive a second timing signal for causing the second transistor to transition between conducting and non-conducting states, and a bulk node coupled to said biasing circuit, the first and second timing signals comprising differential signals;
- and
- a control circuit configured to
- receive at least one feedback signal during application of at least one initial control voltage to said bulk node,
- control said biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the transition, the controlling being based on the at least one feedback signal, and
- control said biasing circuit to apply a second control voltage to said bulk node of said second transistor to adjust the timing of the transition of the second transistor.
A circuit comprising:
- a first transistor having first and second conduction nodes, a control node configured to receive a first timing signal for causing the first transistor to transition between conducting and non-conducting states, and a bulk node;
- a biasing circuit coupled to said bulk node of said first transistor;
- and
- a control circuit configured to
- receive at least one feedback signal during application of at least one initial control voltage to said bulk node,
- control said biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the transition, the controlling being based on the at least one feedback signal, and
- control said biasing circuit to generate the first control voltage to have a constant level to adjust the timing of the transition by a first amount.
A method of modifying timing of at least one of a plurality of transitions between conducting and non-conducting states of a first transistor having first and second conduction nodes, a control node, and a bulk node, the method comprising:
- applying to the control node of said first transistor a first timing signal for causing the first transistor to transition between the conducting and non-conducting states;
- and
- controlling, by a control circuit, a biasing circuit to apply a first control voltage to said bulk node to adjust the timing of the at least one of said plurality of transitions of the first transistor, the controlling being based upon at least one feedback signal received by the control circuit during application of at least one initial control voltage to said bulk node, the controlling comprising operating the biasing circuit to generate the first control voltage to have a constant level to adjust the timing of the at least one of said plurality of transitions by a first amount.
Dependencies are inferred from the claim text.