System and method for interleaved analog-to-digital conversion having scalable self-calibration of timing

A method for adaptive self-calibration to remove sample timing error in time-interleaved analog-to-digital conversion (ADC) of an analog signal comprising:

• establishing a plurality of ADC channels to recursively sample the analog signal within a series of sample segments according to a predetermined sampling clock;
• actuating said ADC channels to generate a time-interleaved series of output samples, the output samples being combinable for digital reconstruction of the analog signal;
• executing a timing skew detection to generate for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment, said timing skew detection generating the timing skew factor for each sample segment based adaptively on the output samples for a selective combination of segments thereabout including at least one preceding sample segment and at least one succeeding sample segment with reference to said sample segment;
• and,
• executing timing control for each of said ADC channels, said timing control adjusting a time delay for the sampling clock within each sample segment responsive to a corresponding one of the timing skew factors generated by said timing skew detection;
• whereby the series of sample segments is aligned substantially with the sampling clock.

A system scalable to a variable multiplicity of channels for adaptive self-calibration to remove synchronization error in time-interleaved analog-to-digital conversion (ADC) of an analog signal comprising:

• a plurality of ADC channels recursively sampling the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples, said ADC channels being actuated in parallel during a sampling cycle upon a frame of sample segments according to correspondingly phase offset versions of the predetermined sampling clock, the output samples being combinable for digital reconstruction of the analog signal;
• a timing skew detection unit coupled to said ADC channels, said timing skew detection unit generating for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment, said timing skew detection unit generating the timing skew factor for the sample segment based adaptively on a rate of change in the analog signal thereat, the timing skew factor being estimated as a difference between the output samples of the immediately preceding and immediately succeeding sample segments;
• wherein said timing skew detection unit includes an error signal generation portion and a timing skew estimator portion coupled thereto, said error signal generation portion including a plurality of digital delay, first digital multiplier, first digital adder, and averaging cells intercoupled for linearly combining and averaging the output samples received from said ADC channels to generate a set of error signals Xk for the frame of sample segments, the set of error signals Xk being defined according to:
• Xk=E{{tilde over (y)}k[n]·[{tilde over (y)}k+1[n]−{tilde over (y)}k−1[n]]},k=1, . . . ,N
• where k represents a channel index iteratively denoting a particular sample segment within the frame of sample segments, n represents a sampling cycle index, N represents the total number of said ADC channels, {tilde over (y)}[n] represents a value of the output sample at a particularly denoted sample segment and sampling cycle n, and E{ } indicates an averaging operation over a plurality of sampling cycles;
• and,
• a plurality of timing control units respectively coupled to said ADC channels, said timing control units adjusting time delays for the sampling clock within respective sample segments responsive to corresponding ones of the timing skew factors generated by said timing skew detection unit;
• whereby the series of sample segments is aligned substantially with the sampling clock.