Continuous phase adjustment based on injection locking
AssigneeOracle International Corporation
InventorsSuwen Yang, Frankie Y. Liu
Life of this patent
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Abstract
A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.
Claims20
A phase-modification circuit, comprising:
- a master oscillator configured to continuously oscillate to provide an output clock;
- an auxiliary oscillator configured to selectively oscillate to provide an auxiliary signal, wherein the auxiliary oscillator is gated by a divided reference clock, wherein the auxiliary signal is in-phase with the divided reference clock, and wherein the divided reference clock is a divided version of a reference clock;
- and
- an injection-locking mechanism configured to selectively couple the auxiliary signal to the master oscillator to continuously correct a phase error of the output clock relative to the divided reference clock so that the phase error is corrected within a half period of the divided reference clock.
An electronic device, comprising a phase-modification circuit, wherein the phase-modification circuit includes:
- a master oscillator configured to continuously oscillate to provide an output clock;
- an auxiliary oscillator configured to selectively oscillate to provide an auxiliary signal, wherein the auxiliary oscillator is gated by a divided reference clock, wherein the auxiliary signal is in-phase with the divided reference clock, and wherein the divided reference clock is a divided version of a reference clock;
- and
- an injection-locking mechanism configured to selectively couple the auxiliary signal to the master oscillator to continuously correct a phase error of the output clock relative to the divided reference clock so that the phase error is corrected within a half period of the divided reference clock.
A method for correcting a phase error of an output clock relative to a divided reference clock, wherein the method comprises:
- providing the output clock using a continuously oscillating master oscillator;
- providing an auxiliary signal using a selectively oscillating auxiliary oscillator, wherein the auxiliary oscillator is gated by the divided reference clock, wherein the auxiliary signal is in-phase with the divided reference clock, and wherein the divided reference clock is a divided version of a reference clock;
- and
- using an injection-locking mechanism, selectively coupling the auxiliary signal to the master oscillator to continuously correct the phase error of the output clock relative to the divided reference clock so that the phase error is corrected within a half period of the divided reference clock.
Dependencies are inferred from the claim text.