Method and apparatus for reducing interference
AssigneeSilicon Laboratories Inc.
InventorsDavid Welland, Donald Kerth, Caiyi Wang
Life of this patent
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Abstract
A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
Claims15
A method of reducing interference present in a circuit formed on an integrated circuit comprising the steps of:
- identifying a conductive trace in a first layer of the integrated circuit, the conductive trace carrying high frequency digital current in the circuit;
- fabricating first and second conductive strips in the proximity of the identified conductive trace to help contain the high frequency current flowing through the conductive trace, wherein the first conductive strip has first and second opposite ends, wherein the first end makes a connection to a reference voltage, and wherein the second end makes no connection;
- fabricating a third conductive strip in a second layer of the integrated circuit above the conductive trace, the third conductive strip oriented substantially parallel to the conductive trace;
- fabricating a first set of vias to couple the first conductive strip to the third conductive strip;
- and
- fabricating a second set of vias to couple the second conductive strip to the third conductive strip.
A conduit for shielding a conductive trace, in a first layer of an integrated circuit, carrying high frequency digital current on a circuit formed on the integrated circuit in order to reduce interference present in the circuit, the conduit comprising:
- first and second conductive strips positioned substantially parallel to the conductive trace;
- a third conductive strip in a second layer of the integrated circuit above the conductive trace, the third conductive strip positioned substantially parallel to the conductive trace;
- a first set of vias to couple the first conductive strip to the third conductive strip;
- a second set of vias to couple the second conductive strip to the third conductive strip;
- and
- a contact connecting the first conductive strip to a reference voltage, wherein the contact is connected to the first conductive strip near an end of the first conductive strip, and wherein the first conductive strip is open at the opposite end.
Dependencies are inferred from the claim text.