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US 9,000,823 B2Granted
3D clock distribution circuits and methods
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorMu-Shan Lin
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.
Claims16
An integrated circuit, comprising:
- a clock source tier including a clock circuit;
- at least two clock tree tiers disposed in a vertical stack with the clock source tier, each of the at least two clock tree tiers including a clock tree circuit;
- and
- a single inductive tier disposed in the vertical stack with the clock source tier and the at least two clock tree tiers, the inductive tier including at least one inductor,
- wherein the clock circuit disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via, and
- wherein at least a portion of the inductor is disposed above a clock destination node of the at least two clock tree tiers.
3 more elements
An integrated circuit, comprising:
- a clock source tier including a clock circuit;
- at least two clock distribution tiers disposed in a vertical stack with the clock source tier, each of the at least two clock distribution tiers including a clock distribution circuit;
- and
- a single inductive tier disposed in the vertical stack with the clock source tier and the at least two clock distribution tiers, the inductive tier including at least one inductor that is at least partially disposed above a clock destination node of the at least two clock distribution tiers,
- wherein the clock circuit disposed in the clock source tier is coupled to the clock distribution circuits disposed in the at least two clock distribution tiers by at least one inter-layer via, and
- wherein a first destination node in a first clock tree tier of the at least two clock distribution tiers is coupled to a second destination node in a second clock distribution tier of the at least two clock distribution tiers by an inter-layer via.
3 more elements
An integrated circuit, comprising:
- a clock source tier including a clock circuit;
- a plurality of clock tree tiers each including at least one clock tree circuit;
- and
- an inductive tier disposed in a vertical stack with the clock source tier and the plurality of clock tree tiers, the inductive tier including at least one inductor that is disposed above a clock destination node of the plurality of clock tree tiers,
- wherein the clock circuit disposed in the clock source tier is coupled to the clock tree circuits disposed in the plurality of clock tree tiers by at least one inter-layer via, and
- wherein a first destination node in a first clock tree tier of the plurality of clock tree tiers is coupled to a second destination node in a second clock tree tier of the plurality of clock tree tiers by an inter-layer via.
3 more elements
Dependencies are inferred from the claim text.