Asymmetric delay circuit
AssigneeMStar Semiconductor, Inc.
InventorsHuimin Tsai, Yu-Min Yeh
Life of this patent
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Abstract
A delay circuit for receiving an input signal and generating a delayed output signal. The delay circuit includes a first delay module and a second delay module. The first delay module includes a first delay unit for generating a first delayed signal according to an input signal and a first logic unit, coupled to the first delay unit, for generating a first delayed output signal according to the first delayed signal and the input signal. The second delay module includes a second delay unit for generating a second delayed signal according to the first delayed output signal and a second logic unit, coupled to the second delay unit, for generating the delayed output signal according to the second delayed signal and the input signal.
Claims6
A memory system comprising:
- a storage device comprising:
- an input port SAE;
- an output port RDY;
- an output port DATA;
- an enable signal generator, coupled to the storage device, for generating an enable signal to the input port SAE;
- and
- a delay circuit, coupled to the storage device and the enable signal generator, for receiving an input signal from the output port RDY and generating a delayed output signal to the enable signal generator, wherein the output port RDY signal provides a falling signal to notify the enable signal generator that a data read operation from the storage device is finished, the delay circuit comprising:
- a first delay module comprising:
- a first delay unit for generating a first delayed signal according to an input signal;
- and
- a first logic unit, coupled to the first delay unit, for generating a first delayed output signal according to the first delayed signal and the input signal;
- and
- a second delay module comprising:
- a second delay unit for generating a second delayed signal according to the first delayed output signal;
- and
- a second logic unit, coupled to the second delay unit, for generating the delayed output signal according to the second delayed signal and the input signal,
- wherein when the input signal transits from a first state to a second state, the delayed output signal is delayed for a first delay time with respect to the input signal;
- and when the input signal transits from the second state to the first state, the delayed output signal is delayed for a second delay time with respect to the input signal, the first delay time and the second delay time being different.
Dependencies are inferred from the claim text.