Apparatuses and methods for altering a forward path delay of a signal path
AssigneeMicron Technology, Inc.
InventorsJongtae Kwak, Kallol Mazumder
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.
Claims17
An apparatus, comprising:
- a signal path including a shift circuit, wherein the shift circuit is configured to increase a forward path delay of the signal path by a number of clock cycles of a clock signal, the number of clock cycles based at least in part on a count value;
- a clock circuit configured to apply a first delay to a reference clock signal to provide the clock signal, wherein the first delay is based on a comparison between a feedback clock signal and the reference signal, wherein the clock circuit is configured to apply a second delay to the clock signal to provide the feedback clock signal;
- and
- a measurement circuit configured to count clock cycles using the reference clock signal and the feedback clock signal to provide the count value,
- wherein the count value is representative of the forward path delay.
An apparatus, comprising:
- a signal path having a forward path delay, the signal path comprising:
- a delay adjustment circuit configured to adjust the forward path delay based on a delay from a clock circuit;
- a shift circuit configured to increase the forward path delay by a number of clock cycles of a clock signal, the number of clock cycles based at least in part on a difference between a desired latency and a count value indicative of the forward path delay;
- and
- a buffer configured to receive an input signal and a signal distribution network configured to provide an output signal, wherein the output signal is a delayed version of the input signal.
A method, comprising:
- determining a count of clock cycles of a clock signal that is indicative of a forward path delay of a signal path by counting clock cycles of the clock signal associated with a propagation delay through the signal path, wherein counting the clock cycles of the clock signal associated with the propagation delay through the signal path includes:
- starting a counter responsive to receiving a start signal that is based on a first clock signal of a clock circuit;
- and
- stopping the counter responsive to receiving a stop signal that is based on a second clock signal of the clock circuit, wherein the second clock signal is delayed relative to the first clock signal;
- and
- increasing the forward path delay of the signal path based on the count of clock cycles, to be equal to a desired latency when the count indicates the forward path delay is less than the desired latency.
Dependencies are inferred from the claim text.