Fractional spur reduction using controlled clock jitter
AssigneeMarvell World Trade Ltd.
InventorsLuca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
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Abstract
In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.
Claims20
An apparatus comprising:
- a clock generator configured to add jitter of a controlled characteristic to a first reference clock to generate a second reference clock;
- and
- a phase locked loop (PLL) configured to generate a local oscillator (LO) signal for a transceiver based on the second reference clock to reduce a fractional spur in the LO signal caused by a radio frequency (RF) signal coupling into the PLL,
- wherein the jitter of the controlled characteristic adds an amount of energy inside a bandwidth of the PLL.
A method comprising:
- generating jitter of a controlled characteristic;
- adding the jitter into a first reference clock to generate a second reference clock;
- generating a local oscillator (LO) signal using a phase-locked loop (PLL) based on the second reference clock to reduce a fractional spur in the LO signal caused by a radio frequency (RF) signal coupling into the PLL,
- wherein the jitter of the controlled characteristic adds an amount of energy inside a bandwidth of the PLL.
Dependencies are inferred from the claim text.