Coarse lock detector
AssigneeSamsung Display Co., Ltd.
InventorsMoon-Sang Hwang, Won-Jun Choe, Han-Kyu Chi, Deog-Kyoon Jeong
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Abstract
A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
Claims19
A coarse lock detector comprising first through p-th detection cells which receive p multiphase clocks generated by incrementally delaying a reference clock, wherein the first through p-th detection cells are divided into a first detection cell group having detection cells defined by 3k+1 of the p-th detection cells, a second detection cell group having detection cells defined by 3s+2 of the p-th detection cells, and a third detection cell group having detection cells defined by 3r of the p-th detection cells, where p is an integer equal to or greater than four, k is an integer equal to or greater than zero when 3k+1 is equal to or smaller than p, s is an integer equal to or greater than zero when 3s+2 is equal to or smaller than p, and r is an integer equal to or greater than one when 3r is equal to or smaller than p, wherein each of the detection cells groups has the same number of cells, wherein at least one detection cell of the first detection cell group is only connected to at least one other detection cell of the first detection cell group, at least one detection cell of the second detection cell group is only connected to at least one other detection cell of the second detection cell group, and at least one detection cell of the third detection cell group is only connected to at least one other detection cell of the third detection cell group.
A coarse lock detector comprising first through P-th detection cells which receive P multiphase clocks generated by incrementally delaying a reference clock, wherein the first through P-th detection cells are divided into first through U-th detection cell groups corresponding to the first through P-th multiphase clocks, wherein each of the first through U-th detection cell groups comprises detection cells defined by (1×A(W)+W)-th through (U×A(W)+W)-th, where U is an integer equal to or greater than four, P is an integer greater than U, W is an integer that satisfies 1≦W≦U, and A(W) is an integer equal to or greater than zero when each of (1×A(W)+W) through (U×A(W)+W) is equal to or less than P, wherein each of the detection cells groups has the same number of cells, wherein at least one detection cell of each of the U-th detection cell groups are only connected to at least one other detection cell of the same U-th detection cell group.
Dependencies are inferred from the claim text.