US 9,000,806 B2 · Preventing A-B-A race in a latch-based device

Abstract

A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.

Claims20

Dependent claims

A method comprising:

determining, by a device, whether a clock gating component is enabled,
the clock gating component being associated with a latch of the device,
a blocking element being included in a logical path from the latch of the device to
a storage element of the device;
and
selectively preventing, by the device and using the blocking element, an output value of the latch from changing or enabling, by the device and using the blocking element, the output value of the latch to change,
the output value of the latch being prevented from changing when the clock gating component is not enabled, and
the output value of the latch being enabled to change when the clock gating component is enabled.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/907,466Filed 31 May 2013 · continuation

Priority

20 Jul 2011

Published

US 2013/0021064 A13 Oct 2013

Granted

7 Apr 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03K 19/096
Using field-effect transistors: synchronous circuits, i.e. using clock signals
G06F 1/3237
Power saving characterised by the action undertaken: by disabling clock generation or distribution
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
H03K 19/0016
Arrangements for reducing power consumption: by using a control or a clock signal, e.g. in order to apply power supply

Family

Application13/187,163Parent of this continuation · filed 20 Jul 2011

US 2013/0257479 A1Pre-grant publication · published 3 Oct 2013

US 8,461,874 B2Parent of this continuation

US 2013/0021064 A1Published application

US 9,000,806 B2This patent

From the US filing history. Foreign family members aren’t listed.

Preventing A-B-A race in a latch-based device

Life of this patent

Preventing A-B-A race in a latch-based device

Life of this patent

Abstract

Claims20