Integrated circuit device comprising clock gating circuitry, electronic device and method for dynamically configuring clock gating
AssigneeFreescale Semiconductor, Inc.
InventorsMichael Priel, Ilan Kapilushnik, Dan Kuzmin
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Abstract
An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled.
Claims20
An integrated circuit comprising clock gating circuitry, wherein the clock gating circuitry comprises:
- a first clock gating component located within a clock distribution network and arranged to enable a first part of the clock distribution network to be gated;
- gating control circuitry arranged to cause the first clock gating component to disable the first part of the clock distribution network upon certain conditions being fulfilled;
- a first clock gating disabling element configurable to enable the first clock gating component to enable the gating of the first part of the clock distribution network, and to receive as inputs a first clock gating control signal and a first clock gating enable signal;
- a second clock gating component arranged to enable a second part of the clock distribution network to be gated;
- and
- a second clock gating disabling element arranged to enable the second clock gating component to enable the gating of the second part of the clock distribution network, and to receive as inputs a second clock gating control signal and a second clock gating enable signal.
A method for dynamically configuring clock gating, the method comprising:
- identifying a first part of a clock distribution network for which clock gating is to be enabled/disabled;
- configuring a first clock gating control signal corresponding to the identified first part of the clock distribution network to be enabled/disabled;
- and
- applying the configured first clock gating control signal and a first clock gating enable signal to a first clock gating disabling element;
- identifying a second part of the dock distribution network for which clock gating is to be enabled/disabled;
- configuring a second clock gating control signal corresponding to the identified second part of the clock distribution network to be enabled/disabled;
- and
- applying the configured second clock gating control signal and a second clock gating enable signal to a second clock gating disabling element.
An electronic device comprising clock gating circuitry;
- the clock gating circuitry comprising:
- a first clock gating component located within a clock distribution network and arranged to enable a first part of the clock distribution network to be gated;
- and
- gating control circuitry arranged to cause the first dock gating component to disable the first part of the clock distribution network upon certain conditions being fulfilled;
- a first clock gating disabling element configured to enable the first clock gating component to enable the gating of the first part of the clock distribution network, and to receive as inputs a first clock gating control signal and a first clock gating enable signal;
- and
- a second clock gating disabling element configured to enable gating of a second part of the clock distribution network, and to receive as inputs a second clock gating control signal and a second clock gating enable signal.
Dependencies are inferred from the claim text.