Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device

An integrated device comprising:

• a combiner circuit;
• a configurable delay line configured to delay at least one of a first data signal generated by a hard logic block and a second data signal generated by a soft logic module and to output a delayed data signal;
• selection circuitry configured to provide to the combiner circuit at least two input signals comprising:
• one of the first data signal, the second data signal, and the delayed data signal;
• and
• one of the first data signal, the second data signal, the delayed data signal, and a zero value signal;
• and
• control logic configured to control which of the first data signal, the second data signal, the delayed data signal, and the zero value signal are selected as the two input signals provided to the combiner circuit,
• wherein the combiner circuit is configured to combine the two input signals provided by the selection circuitry and to output a combined signal.

A method for interfacing between a hard logic portion and a field programmable gate array (“FPGA”) fabric in an integrated device, the method comprising:

• determining, with control logic, which of a hard logic block implemented in the hard logic portion of the integrated device and a soft logic module implemented in the FPGA fabric of the integrated device are to be used for processing an input signal;
• delaying, with a configurable delay line, at least one of a first data signal generated by the hard logic block and a second data signal generated by the soft logic module by a controllable amount of delay to output a delayed data signal;
• responsive to determining that the hard logic block is to be used alone, controlling selection circuitry to provide the first data signal generated by the hard logic block and a zero value signal to a combiner circuit;
• responsive to determining that the soft logic module is to be used alone, controlling selection circuitry to provide the second data signal generated by the soft logic module and the zero value signal to the combiner circuit;
• and
• responsive to determining that the hard logic block and the soft logic module are to be used together, controlling selection circuitry to provide two of the first data signal, the second data signal, and the delayed data signal to the combiner circuit.