Implementation of related clocks
AssigneeTabula, Inc.
InventorsChristopher D. Ebeling, Michael Glenn Wrighton, Andrew Caldwell, Kent Townley
Life of this patent
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Abstract
An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.
Claims21
An integrated circuit (IC) comprising:
- a plurality of configurable circuits for performing a plurality of operations, each operation defined by one of a plurality of different sets of configuration data;
- and
- a reconfiguration counter for providing a reconfiguration state to the configurable circuits, the reconfiguration state for selecting a set of the configuration data from the plurality of sets of configuration data, wherein the reconfiguration counter advances count to a next reconfiguration state when it receives a count enable signal, wherein the count enable signal is modulated so the configurable circuits perform the plurality of operations at a user specified data rate.
An integrated circuit (IC) comprising:
- a first set of reconfigurable circuits for implementing a first clock domain of a user design, wherein the first set of reconfigurable circuits has a first reconfiguration state that loopers at a first rate;
- and
- a second set of reconfigurable circuits for implementing a second clock domain of the user design, wherein the second set of reconfigurable circuits has a second reconfiguration state that loopers at a second rate that is different from the first rate, wherein a particular reconfigurable circuit in the second set of reconfigurable circuits synchronously receives a signal from the first set of reconfigurable circuit.
An integrated circuit (IC) for implementing a user design, the user design comprising:
- a first clock domain operating at a first user clock;
- a second clock domain operating at a second user clock that is different from the first user clock;
- and
- a signal that travels from the first clock domain to a second clock domain at a time slot that is statically scheduled.
Dependencies are inferred from the claim text.