Method to achieve true fail safe compliance and ultra low pin current during power-up sequencing for mobile interfaces
AssigneeTexas Instruments Incorporated
InventorsDevraj Matharampallil Rajagopal, Rajagopalan P
Life of this patent
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Abstract
An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.
Claims20
An input/output (IO) circuit powered by an input/output (IO) supply voltage comprising:
- a supply detector cell configured to detect a core supply voltage and generate a supply detect signal;
- a driver circuit connected to a PAD and configured to receive the supply detect signal;
- and
- a failsafe circuit configured to receive a PAD voltage, wherein the failsafe circuit and the supply detector cell are configured to control a leakage current from the PAD based on the IO supply voltage and the PAD voltage.
An input/output (IO) circuit powered by an input/output (IO) supply voltage comprising:
- a supply detector cell configured to detect a core supply voltage;
- a pair of level shifter circuits, each level shifter circuit is configured to receive an output of the supply detector cell and configured to translate the output of supply detector cell from a core supply voltage level to an IO supply voltage level;
- a pair of predriver logic circuits, each predriver logic circuit is connected to an output of a level shifter circuit;
- a pair of gating circuits, each gating circuit is connected to an output of a predriver logic circuit;
- and
- a failsafe circuit configured to receive a PAD voltage, wherein the failsafe circuit and the supply detector cell are configured to control a leakage current from the PAD based on the supply voltage and the PAD voltage.
A method comprising:
- detecting a core supply voltage;
- configuring a failsafe circuit to control a leakage current from a PAD through de-activation of a final driver circuit when the input/output (IO) supply is below a trip-point voltage and PAD is at logic-HIGH;
- and
- configuring a supply detector cell, when core supply voltage is in OFF state, to control the leakage current from the PAD through de-activation of the final driver circuit when the supply voltage is above a trip-point voltage and PAD is at logic-HIGH.
A computing device comprising:
- a processing unit;
- a memory module coupled to the processing unit;
- a plurality of logic circuits coupled to the processing unit and the memory module;
- and
- an input/output (IO) circuit coupled to at least one logic circuit of the plurality of logic circuits, the IO circuit comprising:
- a supply detector cell configured to detect a core supply voltage and generate a supply detect signal;
- a driver circuit connected to a PAD and configured to receive the supply detect signal;
- and
- a failsafe circuit configured to receive a PAD voltage, wherein the failsafe circuit and the supply detector cell are configured to control a leakage current from the PAD based on the IO supply voltage and the PAD voltage.
Dependencies are inferred from the claim text.