US 9,000,600 B2 · Reduced stress TSV and interposer structures

Abstract

A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.

Claims15

Dependent claims

A structure comprising a microelectronic component comprising circuitry, the microelectronic component comprising a substrate comprising an opening in a top surface;

wherein the circuitry comprises a conductive via in the opening;
wherein the opening comprises a first sidewall of a first material, and the conductive via comprises a second sidewall of a second material;
wherein at least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location, and between the meeting location and the top surface of the substrate the first and second sidewalls are separated by a third material which is a dielectric different from the first material.

Dependencies are inferred from the claim text.

Facts

Application

14/204,860Filed 11 Mar 2014 · continuation

Priority

8 Jun 2012

Published

US 2014/0217607 A17 Aug 2014

Granted

7 Apr 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10W 40/00
Arrangements for thermal protection or thermal control
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0245
The interconnections being through-semiconductor vias: comprising use of blind vias during the manufacture
H10W 20/0261
The interconnections being through-semiconductor vias: characterised by the filling method or the material of the conductive fill

Family

Application13/492,064Parent of this continuation · filed 8 Jun 2012

US 2014/0217607 A1Pre-grant publication · published 7 Aug 2014

US 8,772,946 B2Parent of this continuation

US 2013/0328186 A1Published application

US 9,000,600 B2This patent

From the US filing history. Foreign family members aren’t listed.

Reduced stress TSV and interposer structures

Life of this patent

Reduced stress TSV and interposer structures

Life of this patent

Abstract

Claims15