Multichip integration with through silicon via (TSV) die embedded in package

A system, comprising:

• a circuit board;
• and
• a package assembly coupled with the circuit board via electrical routing features disposed on an outer surface of the package assembly, the package assembly comprising:
• a substrate comprising one or more build-up layers;
• a first die embedded in the substrate, the first die having a first side with one or more transistors, a second side opposite to the first side, a first TSV, and a first electrical routing feature on the second side, the first side electrically coupled with the first electrical routing feature by the first TSV;
• an adhesive layer disposed on the second side of the first die;
• a second die with a second TSV and a second electrical routing feature electrically coupled with the second TSV;
• a die interconnect disposed between the first electrical routing feature and the second electrical routing feature;
• and
• an electrical path including the first TSV and the second TSV, wherein the electrical path is configured to route electrical signals between the second die and the circuit board through the one or more build-up layers.

A package assembly comprising:

• a package substrate with a plurality of build-up layers;
• a first die embedded in the package substrate, the first die having a first side with one or more transistors, a second side opposite to the first side, a first through silicon via (TSV), and an electrical routing feature disposed on a first portion of the second side, wherein the electrical routing feature is electrically coupled with at least one transistor of the one or more transistors by the first TSV;
• an adhesive layer disposed on a second portion of the second side of the first die;
• a second die coupled with the adhesive layer, the second die having a second TSV, wherein the second TSV is electrically coupled with the first TSV;
• and
• an underfill layer disposed between the first die and the second die.

A package assembly comprising:

• a package substrate with a plurality of build-up layers;
• a first die embedded in the package substrate, the first die having a first side with one or more transistors, a second side opposite to the first side, a first through silicon via (TSV), and an electrical routing feature disposed on a first portion of the second side, wherein the electrical routing feature is electrically coupled with at least one transistor of the one or more transistors by the first TSV;
• an adhesive layer disposed on a second portion of the second side of the first die;
• a second die coupled with the adhesive layer, the second die having a second TSV, wherein the second TSV is electrically coupled with the first TSV;
• and
• a layer of molding material configured to encapsulate the second die.