Wafer-level thin chip integration

An electronic device comprising:

• a printed circuit board;
• and
• a wafer level-package device coupled to the printed circuit board, the wafer-level package device including
• an active device wafer having a surface;
• a thin integrated circuit chip device coupled to the active device wafer, where the thin integrated circuit chip has a thickness less than 50 μm;
• an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip;
• a redistribution layer structure coupled to the thin integrated circuit chip;
• and
• at least one solder bump coupled to the redistribution layer structure.

A process comprising:

• placing a thin integrated circuit chip device on a processed active device wafer, where the thin integrated circuit chip includes at least one electrical interconnection to the processed active device wafer and at least one electrical interconnection on a side of the thin integrated circuit chip opposite the processed active device wafer, and where the thin integrated circuit chip has a thickness less than 50 μm;
• forming an encapsulation structure over the active device wafer, the thin integrated circuit chip, and the at least one electrical interconnection;
• exposing a portion of the electrical interconnection;
• forming a redistribution layer structure on the encapsulation structure, where the redistribution layer is electrically coupled to the electrical interconnection;
• and
• forming at least one solder bump on the redistribution layer structure.