# US 9,000,583 B2 · Multiple die in a face down package

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- Number: US 9,000,583 B2
- Document ID: US9000583B2
- Status: Granted
- Kind: B2
- Application number: 14/040,948
- Filed: 2013-09-30
- Published: 2014-05-01
- Granted: 2015-04-07
- Earliest claimed: 2011-08-15
- Assignees: Tessera, Inc.
- Applicants: Tessera, Inc.
- Inventors: Belgacem Haba; Wael Zohni; Richard Dewitt Crisp
- Web page: https://patentgrep.com/patent/US9000583B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/465: {Bumps or wires}
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 76/12: characterised by their shape
- H10W 72/07554: {changes in dispositions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/758: {between a chip and a stacked discrete passive device}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a subassembly including:
a first microelectronic element including a semiconductor chip having a plurality of chip contacts at a front surface thereof, and an electrically conductive redistribution layer at the front surface contacting at least some of the chip contacts, the redistribution layer including redistribution contacts and electrically conductive traces extending along the front surface of the semiconductor chip between the chip contacts and the redistribution contacts;
a second microelectronic element including a second semiconductor chip having a plurality of chip contacts at a front surface thereof, and an electrically conductive redistribution layer at the front surface of the second semiconductor chip contacting at least some of the chip contacts of the second semiconductor chip, the redistribution layer of the second microelectronic element including redistribution contacts and electrically conductive traces extending along the front surface of the second semiconductor chip between the chip contacts of the second semiconductor chip and the redistribution contacts of the redistribution layer of the second microelectronic element, the redistribution contacts of the redistribution layer of the second microelectronic element facing the redistribution contacts of the redistribution layer of the first microelectronic element and being joined thereto; and
a substrate having first and second opposed surfaces, the first surface facing the subassembly, the second surface having terminals thereon for electrical interconnection with an external component; and
leads electrically interconnecting the subassembly with the substrate.

### Claim 2 (depends on 1)

The microelectronic assembly of claim 1, wherein the leads have portions aligned with an opening in the substrate.

### Claim 3 (depends on 1)

The microelectronic assembly of claim 1, wherein the leads include wire bonds extending from the first microelectronic element through an opening in the substrate.

### Claim 4 (depends on 3)

The microelectronic assembly of claim 3, wherein the wire bonds extend from contacts of the first microelectronic element disposed beyond an edge of the second microelectronic element.

### Claim 5 (depends on 1)

The microelectronic assembly of claim 1, wherein the leads include wire bonds extending from contacts at the front surface of the second microelectronic element about an edge of the second microelectronic element, the wire bonds joined to contacts at the first surface of the substrate.