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US 9,000,572 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsHoon Lee, Sang-Bo Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor package substrate may include a first semiconductor chip, a second semiconductor chip, plugs and interconnection terminals. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The first and second semiconductor chips may have corresponding first regions and corresponding second regions. Conductive plugs may be built only in a first region of the first semiconductor chip. Circuitry of the second semiconductor chip may only be electrically connected to the first semiconductor chip through the conductive connectors corresponding to the first regions of the first and second semiconductor chips.
Claims14
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip stacked on the package substrate, the first semiconductor chip including a first region and a second region and having a top surface and bottom surface;
- at least a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a first region and a second region and having a bottom surface facing the top surface of the first semiconductor chip;
- a first plurality of conductive plugs disposed in the first region of the first semiconductor chip;
- and
- a first plurality of conductive connectors disposed between the first plurality of conductive plugs and the second semiconductor chip to electrically connect the first semiconductor chip with circuitry of the second semiconductor chip,
- wherein the first region of the first semiconductor chip corresponds to a respective first region of the second semiconductor chip and the second region of the first semiconductor chip corresponds to a respective second region of the second semiconductor chip,
- wherein circuitry of the second region of the second semiconductor chip is electrically connected to the first semiconductor chip only through conductive connectors corresponding to the first region of the first semiconductor chip and the first region of the second semiconductor chip, and
- wherein the second region of the second semiconductor chip is warped such that the bottom surface of a second semiconductor chip portion at the first region of the second semiconductor chip between at least two of the conductive connectors is substantially parallel to the top surface of the first semiconductor chip at the first region of the first semiconductor chip, and the bottom surface of a second semiconductor chip portion at the second region of the second semiconductor chip is not substantially parallel to the top surface of the first semiconductor chip at the second region of the first semiconductor chip;
- and
- wherein the circuitry of the second region is not electrically connected to terminals at a bottom surface of the second semiconductor chip in the second region of the second semiconductor chip.
8 more elements
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip stacked on the package substrate, the first semiconductor chip including a first region and a second region;
- at least a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a first region and a second region;
- a first plurality of conductive plugs disposed in the first region of the first semiconductor chip;
- and
- a first plurality of conductive connectors disposed between the first plurality of conductive plugs and the second semiconductor chip to electrically connect the first semiconductor chip with circuitry of the second semiconductor chip,
- wherein the first region of the first semiconductor chip corresponds to a respective first region of the second semiconductor chip and the second region of the first semiconductor chip corresponds to a respective second region of the second semiconductor chip,
- wherein circuitry of the second region of the second semiconductor chip is electrically connected to the first semiconductor chip only through conductive connectors corresponding to the first region of the first semiconductor chip and the first region of the second semiconductor chip,
- wherein the second region of the second semiconductor chip comprises a portion of the second semiconductor chip in which a bottom surface of the second semiconductor chip maintains a slope of at least 15 degrees compared to a slope of a top surface of the first semiconductor chip;
- and
- wherein at a second semiconductor chip portion between at least two of the conductive connectors, a bottom surface of the second semiconductor chip has substantially no slope compared to a slope of a top surface of the first semiconductor chip.
8 more elements
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip stacked on the package substrate, the first semiconductor chip including a first region and a second region;
- at least a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a first region and a second region;
- a first plurality of conductive plugs disposed in the first region of the first semiconductor chip;
- and
- a first plurality of conductive connectors disposed between the first plurality of conductive plugs and the second semiconductor chip to electrically connect the first semiconductor chip with circuitry of the second semiconductor chip,
- wherein the first region of the first semiconductor chip is vertically aligned with a respective first region of the second semiconductor chip and the second region of the first semiconductor chip is vertically aligned with a respective second region of the second semiconductor chip,
- wherein circuitry at the second region of the second semiconductor chip is electrically connected to the first semiconductor chip only through conductive connectors corresponding to the first region of the first semiconductor chip and the first region of the second semiconductor chip,
- wherein the second region of the second semiconductor chip is warped such that at least a portion of a bottom surface of the second semiconductor chip maintains a slope of at least 15 degrees compared to a slope of a top surface of the first semiconductor chip;
- and
- wherein the first region of second semiconductor chip is not warped.
8 more elements
Dependencies are inferred from the claim text.