Semiconductor device and structure
OwnerZvi Or-Bach, Deepak C. Sekar +1inventors
InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Abstract
A device including a first layer of first transistors interconnected by at least one first interconnection layer, where the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, where the second layer is less than about 2 micron thick, where the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, where the connection path includes at least one through-layer via, where the at least one through-layer via is formed through and in direct contact with a source or drain of at least one of the second transistors.
Claims18
A device comprising:
- a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;
- a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than about 2 micron thick, wherein said second layer has a coefficient of thermal expansion;
- and
- a connection path connecting at least one of said second transistors to said first interconnection layer,
- wherein said connection path comprises at least one through-layer via,
- wherein said at least one through-layer via is formed through and in direct contact with a source or drain of at least one of said second transistors, and
- wherein said through-layer via comprises material whose co-efficient of thermal expansion is within about 50 percent of said second layer coefficient of thermal expansion.
A device comprising:
- a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;
- a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than about 2 micron thick;
- and
- a connection path connecting at least one of said second transistors to said first interconnection layer,
- wherein said connection path comprises at least one through-layer via, and
- wherein said at least one through-layer via is formed through and in direct contact with a source or drain of at least one of said second transistors,
- wherein said second layer further comprises a region of high quality oxide isolation,
- wherein said high quality oxide isolation has a leakage of less than about one picoamp per micron at device power supply and about 25° C.
A device comprising:
- a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;
- a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than about 2 micron thick;
- and
- a connection path connecting at least one of said second transistors to said first interconnection layer,
- wherein said connection path comprises at least one through-layer via,
- wherein said at least one through-layer via is formed through and in direct contact with a source or drain of said at least one of said second transistors.
A device comprising:
- a first layer of first transistors interconnected by at least one first interconnection layer, wherein said first interconnection layer comprises copper or aluminum;
- a second layer comprising second transistors, said second layer overlaying said first interconnection layer, wherein said second layer is less than about 2 micron thick;
- and
- a connection path connecting at least one of said second transistors to said first interconnection layer,
- wherein said connection path comprises at least one through-layer via, and
- wherein said first layer comprises at least one first alignment mark, and
- wherein at least one of said second transistors is aligned at least partially to said first alignment mark, and
- wherein said second layer further comprises a region of high quality oxide isolation,
- wherein said high quality oxide isolation has a leakage current of less than about one picoamp per micron at device power supply and about 25° C.
Dependencies are inferred from the claim text.