# US 9,000,556 B2 · Lateral etch stop for NEMS release etch for high density NEMS/CMOS monolithic integration

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,000,556 B2
- Document ID: US9000556B2
- Status: Granted
- Kind: B2
- Application number: 13/269,552
- Filed: 2011-10-07
- Published: 2013-04-11
- Granted: 2015-04-07
- Earliest claimed: 2011-10-07
- Assignees: International Business Machines Corporation
- Applicants: Josephine B. Chang; Leland Chang; Sebastian U. Engelmann; Michael A. Guillorn
- Inventors: Josephine B. Chang; Leland Chang; Sebastian U. Engelmann; Michael A. Guillorn
- Web page: https://patentgrep.com/patent/US9000556B2

## CPC

- B81C 1/0023: {Packaging together an electronic processing unit die and a micromechanical structure die (MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261)}
- B81C 1/00801: {Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer (B81C1/00595, B81C1/00468 take precedence)}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- B81B 2207/015: the micromechanical device and the control or processing electronics being integrated on the same substrate
- B81C 2203/0714: Forming the micromechanical structure with a CMOS process
- B81C 2203/0742: Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
- H10W 74/016: {using moulds}
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

## Claims

### Claim 1

An integrated semiconductor device structure, comprising:
a substrate;
an electromechanical device including an anchor and a cantilever beam connected to the anchor, the anchor and the cantilever beam positioned above the substrate, the cantilever beam extending from the anchor and is enabled for mechanical movement;
a complementary metal oxide semiconductor (CMOS) device proximate the electromechanical device and positioned on the substrate;
a protective layer encapsulating the electromechanical device, a portion of the protective layer positioned directly below the anchor and between the anchor and the substrate; and
a barrier layer separating the electromechanical device and the CMOS device, wherein the barrier layer has a higher etch grade than the protective layer.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein the substrate is a silicon-on-insulator (SOI) substrate.

### Claim 3 (depends on 2)

The semiconductor device structure of claim 2, wherein the protective layer is Silicon Dioxide (SiO2).

### Claim 4 (depends on 1)

The semiconductor device structure of claim 1, wherein the electromechanical device is a nanoelectromechanical system (NEMS).

### Claim 5 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer intersects a plane below the electromechanical device and the CMOS device.

### Claim 6 (depends on 1)

The semiconductor device structure of claim 1, wherein the electromechanical device and the CMOS device are separated by a distance no greater than 250 nanometers.

### Claim 7 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer is amorphous carbon.

### Claim 8 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer is Carbon Nitride (C3N4).

### Claim 9 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer is a plasma deposited fluorocarbon.

### Claim 10 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer is a carbon-based polymer.

### Claim 11 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer is Tantalum Nitride (TaN).

### Claim 12 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer is Titanium Nitride (TiN).

### Claim 13 (depends on 1)

The semiconductor device structure of claim 1, wherein the barrier layer is Hafnium Oxide (HfO2).

### Claim 14 (depends on 1)

The semiconductor device structure of claim 1, wherein the electromechanical device is positioned directly on the substrate.

### Claim 15 (depends on 1)

The semiconductor device structure of claim 1, wherein the protective layer encapsulates the electromechanical device by covering all exposed surfaces of the electromechanical device.

### Claim 16

An integrated semiconductor device structure, comprising:
a substrate;
a complementary metal oxide semiconductor (CMOS) device positioned on the substrate;
wiring coupled to the COM device;
a contact extending from the wiring down toward the substrate;
an electromechanical device including an anchor and a cantilever beam connected to the anchor, the anchor coupled to the contact, the anchor and the cantilever beam positioned above the substrate, the cantilever beam extending from the anchor and is enabled for mechanical movement;
a protective layer encapsulating the electromechanical device, a portion of the protective layer positioned directly below the anchor and between the anchor and the substrate; and
a barrier layer separating the electromechanical device and the CMOS device, wherein the barrier layer has a higher etch grade than the protective layer.

### Claim 17 (depends on 16)

The semiconductor device structure of claim 16, wherein the substrate is a silicon-on-insulator (SOI) substrate.

### Claim 18 (depends on 16)

The semiconductor device structure of claim 16, wherein the electromechanical device is a nanoelectromechanical system (NEMS).

### Claim 19 (depends on 16)

The semiconductor device structure of claim 16, wherein the barrier layer intersects a plane below the electromechanical device and the CMOS device.

### Claim 20 (depends on 16)

The semiconductor device structure of claim 16, wherein the electromechanical device and the CMOS device are separated by a distance no greater than 250 nanometers.

### Claim 21 (depends on 16)

The semiconductor device structure of claim 16, wherein the barrier layer is amorphous carbon.

### Claim 22 (depends on 16)

The semiconductor device structure of claim 16, wherein the barrier layer is Carbon Nitride (C3N4).