Back to results
US 9,000,539 B2Granted
Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
AssigneeTexas Instruments Incorporated
InventorsManoj Mehrotra, Hiroaki Niimi
Life of this patent
Estimating the term…
Abstract
The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.
Claims6
A method of forming a semiconductor structure comprising:
- forming a gate structure that touches a semiconductor region, the gate structure having a sacrificial gate dielectric and a sacrificial gate, the sacrificial gate dielectric touching the semiconductor region, the sacrificial gate touching the sacrificial gate dielectric, the semiconductor region having a conductivity type;
- etching away a portion of the sacrificial gate dielectric to form a sacrificial dielectric structure and a cavity, the sacrificial dielectric structure touching the sacrificial gate and the semiconductor region, the cavity lying directly vertically below a portion of the sacrificial gate;
- forming a source and a drain that touch the semiconductor region after the sacrificial dielectric structure has been formed, the source and the drain each having a conductivity type that is opposite the conductivity type of the semiconductor region;
- forming a conformal etch resistant layer on exposed surfaces of the sacrificial gate and sacrificial dielectric structure including within the cavity;
- forming a non-conductive layer over the conformal etch resistant layer, the non-conductive layer filling the cavity;
- and
- forming a sidewall spacer from the conformal etch resistant layer and the non-conductive layer.
4 more elements
A method of forming a semiconductor structure comprising:
- forming a sacrificial gate dielectric layer over a semiconductor region;
- forming a sacrificial gate over the sacrificial gate dielectric layer;
- etching the sacrificial gate dielectric layer to undercut the sacrificial gate dielectric layer from the sacrificial gate to create a cavity, the cavity lying directly vertically below a portion of the sacrificial gate;
- forming a conformal etch resistant layer on exposed surfaces of the sacrificial gate and sacrificial gate dielectric layer including within the cavity;
- forming a non-conductive layer over the conformal etch resistant layer, the non-conductive layer filling the cavity;
- forming a sidewall spacer from the conformal etch resistant layer and the non-conductive layer;
- forming a source and a drain that touch the semiconductor region;
- removing the sacrificial gate and sacrificial gate dielectric layer to expose the conformal etch resistant layer;
- forming a gate dielectric layer on the conformal etch resistant layer;
- and
- forming a metal gate on the gate dielectric layer, such that the conformal etch resistant layer extends along the gate dielectric layer from a top region of the metal gate to the semiconductor region.
8 more elements
A method of forming a semiconductor structure comprising:
- forming a sacrificial gate dielectric layer over a semiconductor region;
- forming a polysilicon gate layer over the sacrificial gate dielectric layer;
- patterning the sacrificial gate dielectric layer and polysilicon gate layer to form a sacrificial gate structure including a sacrificial gate dielectric and a sacrificial gate;
- etching the sacrificial gate dielectric to undercut the sacrificial gate dielectric from the sacrificial gate to create a cavity, the cavity lying directly vertically below a portion of the sacrificial gate;
- forming a conformal nitride layer on vertical and horizontal surfaces of the sacrificial gate and on vertical surfaces of the sacrificial gate dielectric including within the cavity;
- forming an oxide layer over the conformal nitride layer, the oxide layer filling the cavity;
- forming a sidewall spacer from the conformal nitride layer and the oxide layer;
- forming a source and a drain that touch the semiconductor region;
- removing the sacrificial gate and sacrificial gate dielectric to expose the conformal nitride layer;
- forming a gate dielectric layer on the conformal nitride layer;
- and
- forming a metal gate on the gate dielectric layer, such that the conformal nitride layer surrounds the gate dielectric layer and the metal gate from a top region of the metal gate to the semiconductor region.
9 more elements
Dependencies are inferred from the claim text.