US 9,000,537 B2Granted

FinFET devices having recessed liner materials to define different fin heights

AssigneesGlobalfoundries Inc., International Business Machines Corporation

InventorsXiuyu Cai, Ruilong Xie, Kangguo Cheng, Ali Khakifirooz

Life of this patent

Estimating the term…

Loading patent…

Abstract

One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

Claims17

Dependent claims

A FinFET device, comprising;

a plurality of trenches formed in a semiconducting substrate that define at least a first fin and a second fin;
a first local isolation region positioned in a bottom of each of a plurality of trenches that define said first fin, said first local isolation defining a first height of the first fin, said first isolation region comprising a first generally U-shaped liner material having a plurality of spaced apart generally upstanding legs that define, in part, a first cavity, said legs of said first generally U-shaped liner material having a first thickness;
a second local isolation region positioned in a bottom of each of a plurality of trenches that define said second fin, said second local isolation region defining a second fin height, wherein said first and second heights are different, said second local isolation region comprising a second generally U-shaped liner material having a plurality of spaced apart generally upstanding vertically oriented legs that define, in part, a second cavity, said legs of said second generally U-shaped liner material having a second thickness that is different than said first thickness;
a layer of insulating material positioned at least partially in said first and second cavities;
and
a gate structure positioned around a portion of said first and second fins.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/333,683Filed 17 Jul 2014 · division
Priority: 8 Jan 2013
Published: US 2014/0191324 A16 Nov 2014
Granted: 7 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
H10D 30/021
Manufacture or treatment: of FETs having insulated gates [IGFET]
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]

Family

Application13/736,294Parent of this division · filed 8 Jan 2013
US 2014/0327089 A1Pre-grant publication · published 6 Nov 2014
US 8,835,262 B2Parent of this division
US 2014/0191324 A1Published application
US 9,000,537 B2This patent

From the US filing history. Foreign family members aren’t listed.