Device and methods for high-K and metal gate stacks
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Cheng Wu, Po-Nien Chen, Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang
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Abstract
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
Claims8
A semiconductor device, comprising:
- a semiconductor substrate;
- isolation features to separate different regions on the substrate;
- a p-type field-effect transistor (pFET) core region having a first gate stack on the substrate, the first gate stack including an interfacial layer, a high k (HK) dielectric layer on the interfacial layer, and a capping layer of a first material on the HK dielectric layer;
- an input/output pFET (pFET IO) region having a second gate stack on the substrate, the second gate stack including a dielectric layer, an interfacial layer in direct contact with the dielectric layer, a HK dielectric layer on the interfacial layer, and a capping layer of the first material on the HK dielectric layer;
- an n-type field-effect transistor (nFET) core region having a third gate stack on the substrate, the third gate stack including an interfacial layer, a HK dielectric layer on the interfacial layer, and a capping layer of a second material on the HK dielectric layer;
- an input/output nFET (nFET IO) region having a fourth gate stack on the substrate, the fourth gate stack including a dielectric layer, an interfacial layer in direct contact with the dielectric layer, a HK dielectric layer on the interfacial layer, and a capping layer of the second material on the HK dielectric layer;
- and
- a high-resistor region having a fifth gate stack on the substrate, the fifth gate stack including an interfacial layer, a HK dielectric layer on the interfacial layer, and a capping layer of the second material on the HK dielectric layer.
A semiconductor device, comprising:
- a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor;
- an oxide layer on the IO regions of the substrate;
- an interfacial layer on the substrate and in direct contact with the oxide layer;
- a high-k (HK) dielectric layer on the interfacial layer;
- a capping layer of a second material over the HK dielectric layer;
- a work function (WF) metal layer on the capping layer of the second material;
- and
- a polysilicon layer on the WF metal layer.
Dependencies are inferred from the claim text.