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US 9,000,525 B2Granted
Structure and method for alignment marks
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Chang Wen, Hsien-Cheng Wang, Chun-Kuang Chen
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Abstract
The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.
Claims20
A semiconductor structure, comprising:
- a semiconductor substrate having a device region and an alignment region;
- a plurality of gate stacks formed on the semiconductor substrate in the alignment region and configured as an alignment mark, wherein the plurality of gate stacks include a first gate stack and a second gate stack;
- doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks, wherein the doped features include a source/drain feature continuously extending within the semiconductor substrate from an edge of the first gate stack to an edge of the second gate stack, wherein the doped features have a refractive index of about 3;
- and
- channel regions underlying the plurality of gate stacks and free of well dopant, the well dopant being located in the device region.
2 more elements
A semiconductor structure having an alignment mark, comprising:
- a semiconductor substrate having a device region and an alignment region;
- a field-effect device formed within the device region, including:
- a first gate stack formed on the semiconductor substrate;
- a first source and drain regions formed in the semiconductor substrate and disposed on both sides of the first gate stack;
- and
- a first channel region having a channel doped feature formed in the semiconductor substrate and underlying the gate stack;
- and
- an alignment mark formed within the alignment region, including:
- a second gate stack and a third gate stack formed on the semiconductor substrate;
- a second source and drain region formed in the semiconductor substrate and continuously extending within the semiconductor substrate from an edge of the second gate stack to an edge of the third gate stack;
- and
- a second channel region free of channel doped feature in the semiconductor substrate and underlying the second gate stack, and
- wherein the semiconductor substrate includes silicon and the second source and drain regions have a refractive index of about 3.
10 more elements
A method comprising:
- providing a semiconductor substrate having a device region and an alignment region;
- performing a first ion implantation to the semiconductor substrate within the device region while the alignment region is covered by an implantation mask layer;
- thereafter forming a first polysilicon gate stack in a device region and a second polysilicon gate stack in an alignment region;
- thereafter performing a second ion implantation to the semiconductor substrate within the device region and within the alignment region, wherein performing the second ion implantation modifies a refractive index of the semiconductor substrate and increases a wafer quality of an alignment signal from the alignment region to be greater than 1%;
- and
- replacing the first and second polysilicon gate stacks with metal gate stacks.
3 more elements
Dependencies are inferred from the claim text.