Method and apparatus for modeling multi-terminal MOS device for LVS and PDK
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChau-Wen Wei, Cheng-Te Chang, Chin-yuan Huang, Chih Ming Yang, Yi-Kan Cheng
Life of this patent
Estimating the term…
Abstract
An apparatus comprises two n-type metal oxide semiconductor (MOS) devices formed next to each other. Each n-type MOS device further includes a pair of face-to-face diodes formed in an isolation ring. A method of modeling the apparatus comprises reusing four-terminal MOS device models in standard cell libraries and combining the four-terminal MOS device model and the isolation ring model into a 4T MOS plus isolation ring model. The method of modeling the apparatus further comprises adding a dummy device between a body contact of the first n-type MOS device and a body contact of the second n-type MOS device.
Claims13
An apparatus comprising:
- a first n-type metal oxide semiconductor (MOS) device comprising:
- a first drain formed on a first p-type well;
- a first gate;
- a first source formed on the first p-type well;
- a first body contact formed on the first p-type well;
- and
- a first deep n-type well formed between the first p-type well and a p-type substrate;
- a second n-type MOS device formed adjacent to the first n-type MOS device comprising:
- a second drain formed on a second p-type well;
- a second gate;
- a second source formed on the second p-type well;
- a second body contact formed on the second p-type well;
- and
- a second deep n-type well formed between the second p-type well and the p-type substrate, wherein the second deep n-type well and the first deep n-type well are separated by the p-type substrate;
- and
- a dummy device formed between the first body contact and the second body contact, wherein the first body contact is surrounded by a first isolation tub laterally and longitudinally and the second body contact is surrounded by a second isolation tub laterally and longitudinally, and wherein the dummy device is across the first isolation tub and the second isolation tub, and wherein the dummy device is connected to a first voltage potential through a first diode and connected to a second voltage potential through a second diode, and wherein the first voltage potential is different from the second voltage potential.
A semiconductor structure comprising:
- a p-type substrate;
- a first deep n-type well region, a first n-type well region formed on the p-type substrate;
- a first p-type well formed within a first isolation tub formed by the first deep n-type well region and the first n-type well region;
- a first drain region, a first source region and a first body contact region formed in the first p-type well;
- a first gate electrode formed over the first P-type well;
- a second deep n-type well region, a second n-type well region formed on the p-type substrate, wherein the second deep n-type well and the first deep n-type well are separated by a p-type region;
- a second p-type well formed within a second isolation tub formed by the second deep n-type well region and the second n-type well region;
- a second drain region, a second source region and a second body contact region formed in the second p-type well;
- a second gate electrode formed over the second P-type well;
- and
- a dummy device connected between the first body contact region and the second body contact region, wherein the dummy device is across the first isolation tub and the second isolation tub, and wherein the dummy device is connected to a first voltage potential through a first diode and connected to a second voltage potential through a second diode, and wherein the first voltage potential is different from the second voltage potential.
Dependencies are inferred from the claim text.