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US 9,000,512 B1Granted
Packaging of electronic circuitry
AssigneeInternational Rectifier Corporation
InventorsFlorian Bieck, Robert J. Montgomery
Life of this patent
Estimating the term…
Abstract
An assembler receives a circuit device and a mass of conductive material such as a diode, metal material, etc. The assembler bonds a first facing of a circuit device to a substrate. Adjacent to the circuit device, the assembler bonds a first facing of the mass of conductive material to the substrate. The assembler applies an overmold layer of insulation material over the substrate adjacent the circuit device and the mass of conductive material. Subsequent to applying the overmold layer of insulation material, the assembler provides a conductive link between a second facing of the circuit device and a second facing of the mass of conductive material.
Claims23
A multi-layer wafer level assembly comprising:
- a first layer, the first layer including a temporary fabrication substrate;
- a second layer coupled to a facing of the first layer, the second layer including:
- a mass of conductive material, a circuit device, and insulation material;
- a thickness of the circuit device extending from a first surface region on the facing of the first layer to an exposed surface facing of the second layer, the exposed surface facing disposed on the second layer opposite a respective surface of the second layer coupled to the facing of the first layer;
- a thickness of the mass of conductive material extending from a second surface region on the facing of the first layer to the exposed surface facing of the second layer;
- the insulation material disposed in the second layer between the circuit device and the mass of conductive material;
- and
- wherein the exposed surface facing of the second layer is openly accessible to apply an electrically conductive link on the exposed surface facing between the circuit device and the conductive material.
5 more elements
A multi-layer wafer level assembly comprising:
- a first layer, the first layer including a temporary fabrication substrate;
- a second layer coupled to a facing of the first layer, the second layer including:
- a mass of conductive material, a circuit device, and insulation material;
- a thickness of the circuit device extending from a first surface region on the facing of the first layer to an exposed surface facing of the second layer, the exposed surface facing disposed on the second layer opposite a respective surface of the second layer coupled to the facing of the first layer;
- a thickness of the mass of conductive material extending from a second surface region on the facing of the first layer to the exposed surface facing of the second layer;
- the insulation material disposed in the second layer between the circuit device and the mass of conductive material;
- wherein the circuit device is a preliminary fabrication of a vertical field effect transistor device;
- wherein a gate node of the vertical field effect transistor substantially contacts the first surface region on the facing of the first layer;
- wherein a source node of the vertical field effect transistor substantially contacts the second surface region on the facing of the first layer;
- and
- wherein a side of the vertical field effect transistor is accessible from the exposed surface facing of the second layer to create a drain node of the vertical field effect transistor device.
8 more elements
A multi-layer wafer level assembly comprising:
- a first layer, the first layer including a temporary fabrication substrate;
- a second layer coupled to a facing of the first layer, the second layer including:
- a mass of conductive material, a circuit device, and insulation material;
- a thickness of the circuit device extending from a first surface region on the facing of the first layer to an exposed surface facing of the second layer, the exposed surface facing disposed on the second layer opposite a respective surface of the second layer coupled to the facing of the first layer;
- a thickness of the mass of conductive material extending from a second surface region on the facing of the first layer to the exposed surface facing of the second layer;
- the insulation material disposed in the second layer between the circuit device and the mass of conductive material;
- wherein the circuit device is an initial fabrication of a vertical field effect transistor device, the initial fabrication of the vertical field effect transistor device including a gate node and a source node but lacking a drain node;
- wherein the gate node of the vertical field effect transistor contacts the first surface region of the first layer;
- and
- wherein the source node of the vertical field effect transistor contacts the second surface region of the first layer.
7 more elements
A multi-layer wafer level assembly comprising:
- a first layer, the first layer including a temporary fabrication substrate;
- a second layer coupled to the first layer, the second layer including:
- a mass of electrically conductive material, a circuit device, and insulation material;
- the circuit device including a gate node and a source node but lacking a drain node;
- the insulation material disposed in the second layer between the circuit device and the mass of electrically conductive material;
- a thickness of the circuit device extending from a first surface region on an unexposed facing of the first layer to an exposed surface facing of the second layer disposed opposite the unexposed facing of the first layer;
- a thickness of the mass of conductive material extending from a second surface region on the unexposed facing of the first layer to the exposed surface facing of the second layer opposite the unexposed facing of the first layer;
- and
- a thickness of the insulation material extending from a third surface region on the unexposed facing of the first layer to the exposed surface facing of the second layer opposite the unexposed facing of the first layer.
6 more elements
Dependencies are inferred from the claim text.