US 9,000,504 B2Granted

Nonvolatile semiconductor memory device and method for manufacturing same

AssigneeKabushiki Kaisha Toshiba

InventorsShigeki Hattori, Reika Ichihara, Masaya Terai, Hideyuki Nishizawa, Tsukasa Tada, Koji Asakawa, Hiroyuki Fuke, Satoshi Mikoshiba, Yoshiaki Fukuzumi, Hideaki Aochi

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Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.

Claims16

Dependent claims

A nonvolatile semiconductor memory device comprising:

a stacked structure body including
a first electrode film,
a second electrode film apart from the first electrode film in a first direction, and
an inter-electrode insulating film provided between the first electrode film and the second electrode film,
the first electrode film having a first face opposed the inter-electrode insulating film and a first side face intersecting the first face,
the second electrode film having a second face opposing the inter-electrode insulating film and a second side face intersecting the second face, and
the inter-electrode insulating film having a third side face and a fourth side face apart from the third side face in a second direction perpendicular to the first direction;
a semiconductor layer opposed to the first side face, the second side face and the third side face;
an organic film including
a first portion provided between the first side face and the semiconductor layer,
a second portion provided between the second side face and the semiconductor layer,
a third portion provided between the first face and the inter-electrode insulating film,
a fourth portion provided between the second face and the inter-electrode insulating film, and
a fifth portion opposing the fourth side face,
the third portion continuing the first portion, the fifth portion continuing the third portion, the fourth portion continuing the fifth portion, the second portion continuing the fourth portion, and the organic film containing an organic compound;
a semiconductor-side insulating film provided between the organic film and the semiconductor layer;
and
an electrode-side insulating film provided at a first position between the organic film and the first side face, at a second position between the organic film and the first face, at a third position between the organic film and the fourth side face, at a fourth position between the organic film and the second face, and at a fifth position between the organic film and the second side face,
wherein the organic film is bonded to the semiconductor-side insulating film by at least one of an ether linkage, a silyl ether linkage, an ester linkage, and a thioether linkage.

16 more elements

A nonvolatile semiconductor memory device comprising:

a stacked structure body including
a first electrode film,
a second electrode film apart from the first electrode film in a first direction, and
an inter-electrode insulating film provided between the first electrode film and the second electrode film,
the first electrode film having a first face opposed the inter-electrode insulating film and a first side face intersecting the first face,
the second electrode film having a second face opposing the inter-electrode insulating film and a second side face intersecting the second face, and
the inter-electrode insulating film having a third side face and a fourth side face apart from the third side face in a second direction perpendicular to the first direction;
a semiconductor layer opposed to the first side face, the second side face and the third side face;
an organic film including
a first portion provided between the first side face and the semiconductor layer,
a second portion provided between the second side face and the semiconductor layer,
a third portion provided between the first face and the inter-electrode insulating film,
a forth portion provided between the second face and the inter-electrode insulating film, and
a fifth portion opposing the fourth side face,
the third portion continuing the first portion, the fifth portion continuing the third portion, the fourth portion continuing the fifth portion, the second portion continuing the fourth portion, and the organic film containing an organic compound;
a semiconductor-side insulating film provided between the organic film and the semiconductor layer;
and
an electrode-side insulating film provided at a first position between the organic film and the first side face, at a second position between the organic film and the first face, at a third position between the organic film and the fourth side face, at a fourth position between the organic film and the second face, and at a fifth position between the organic film and the second side face,
wherein the organic film is bonded to the electrode-side insulating film by at least one of an ether linkage, a silyl ether linkage, an ester linkage, and a thioether linkage.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/105,565Filed 13 Dec 2013 · division
Priority: JP 2010-25238110 Nov 2010
Published: US 2014/0097485 A110 Apr 2014
Granted: 7 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 64/685
Having a compositional variation, e.g. multilayered: being perpendicular to the channel plane
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND

Family

Application13/234,657Parent of this division · filed 16 Sep 2011
US 2014/0097485 A1Pre-grant publication · published 10 Apr 2014
US 8,633,526 B2Parent of this division
US 2012/0112171 A1Published application
US 9,000,504 B2This patent

From the US filing history. Foreign family members aren’t listed.