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US 9,000,491 B2Granted
Layer formation with reduced channel loss
AssigneeSTMicroelectronics S.r.l.
InventorsNicolas Loubet, Qing Liu, Prasanna Khare
Life of this patent
Estimating the term…
Abstract
Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
Claims26
A device comprising:
- a semiconductor device region;
- a gate region coupled to an upper surface of said semiconductor device region and extending upwardly from the upper surface to define a plurality of gate sidewalls;
- a source region coupled to the upper surface of said semiconductor device region laterally adjacent said gate region, said source region having a proximal end adjacent said gate region and an enlarged height distal end;
- a drain region coupled to the upper surface of said semiconductor device region laterally adjacent said gate region, said drain region having a proximal end adjacent said gate region and an enlarged height distal end;
- a first insulating layer above the semiconductor device region and coupled to the sidewalls of said gate region and an upper surface of the proximal end of said source and drain regions;
- and
- a second insulating layer coupled to the distal end of said source and drain regions, an upper surface of said gate region, said first insulating layer, and a lower surface of said semiconductor device region;
- wherein a portion of the semiconductor device region under said first and second insulating layers is doped.
5 more elements
A device comprising:
- a transistor formed on a bulk semiconductor substrate, the transistor comprising
- a channel region
- a gate electrode structure formed on the channel region, the gate electrode structure including a gate dielectric layer and a conductive gate electrode material layer,
- a gate spacer structure formed on at least two sidewalls of the gate electrode structure,
- a doped source region coupled to the channel region, the doped source region having a proximate source end extending from the channel region under the gate spacer structure, the doped source region having a distal source end located farther from the channel region than the proximate source end, wherein a portion of the distal source end is located adjacent to a first portion of the gate spacer structure and is raised relative to the channel region,
- a doped drain region coupled to the channel region, the doped drain region having a proximate drain end extending from the channel region under the gate spacer structure, and the doped drain region having a distal drain end located farther from the channel region than the proximate drain end, wherein a portion of the distal drain end is located adjacent to a second portion of the gate spacer structure and is raised relative to the channel region,
- a first conformal insulating material layer formed over the gate electrode structure, included as part of the gate spacer structure, formed around at least part of the distal source end, formed around at least part of the distal drain end, and formed below at least part of the channel region,
- a first portion of a second insulating material layer included as part of the gate spacer structure over the first insulating material layer,
- a second portion of the second insulating material layer formed on a side of and at least partially below the distal source end over the first insulating material layer, and
- a third portion of the second insulating material layer formed on a side of and at least partially below the distal drain end over the first insulating material layer.
7 more elements
A device comprising:
- a transistor formed on a bulk semiconductor substrate, the transistor comprising
- a gate electrode structure formed on a channel region, the gate electrode structure including a gate dielectric layer and a conductive gate electrode material layer,
- a gate spacer structure formed on at least two sidewalls of the gate electrode structure,
- a doped source region coupled to the channel region, the doped source region having a proximate source end extending from the channel region under the gate spacer structure, and the doped source region having a distal source end located farther from the channel region than the proximate source end, wherein a portion of the distal source end is located adjacent to a first portion of the gate spacer structure and is raised relative to the channel region,
- a doped drain region coupled to the channel region, the doped drain region having a proximate drain end extending from the channel region under the gate spacer structure, and the doped drain region having a distal drain end located farther from the channel region than the proximate drain end, wherein a portion of the distal drain end is located adjacent to a second portion of the gate spacer structure and is raised relative to the channel region,
- a first portion of a second insulating material layer included as part of the gate spacer structure,
- a second portion of the second insulating material layer formed on a side of and at least partially below the distal source end, and
- a third portion of the second insulating material layer formed on a side of and at least partially below the distal drain end.
5 more elements
Dependencies are inferred from the claim text.