Random access memory cells using spatial wavefunction switched field-effect transistors
OwnerPawan Gogna, Faquir Chand Jain +2inventors
InventorsPawan Gogna, Faquir Chand Jain, John Chandy, Evan Heller
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Abstract
Multi-source/drain Spatial Wavefunction Switched (SWS) field-effect transistors (FETs) are configured to serve as 1-bit and 2-bit static random access memory (SRAM) and dynamic random access memory (DRAM) cells. The SWS-FET transport channel comprises of multiple asymmetric coupled wells which are contacted via more than one sources and drains.
Claims6
A 1-bit Static Random Access Memory (SRAM) cell, comprising:
- two Spatial Wavefunction Switched (SWS) field-effect transistors (FETs),
- wherein said SWS-FETs comprise of at least two quantum well channels with appropriate barrier layers separating quantum wells, gate insulator layer, and gate contact layer, realized on appropriate substrate with buffer layers,
- said quantum well channels comprising of at least two sources and one drain,
- said sources are connected to two voltage sources with different magnitudes,
- the gate of first SWS-FET is connected to the drain of second SWS-FET,
- the gate of second SWS-FET is connected to the drain of first SWS-FET,
- the gates of said two SWS-FETs connected to one end of channel of two access transistors,
- the said access transistors are conventional FETs,
- the other end of channel of conventional access FET is connected to Bitline and Bitline-Bar,
- the gates of said access transistors are connected to Wordline,
- said wordline access the stored bit depending on the voltage level applied to it.
A 2-bit Static Random Access Memory (SRAM) cell, comprising:
- two Spatial Wavefunction Switched (SWS) FETs,
- wherein said SWS-FETs comprise of at least four quantum well channels with appropriate barrier layers separating quantum wells, gate insulator layer, and gate contact layer, realized on appropriate substrate with buffer layers,
- said quantum well channels comprising of at least four sources and one drain,
- said sources are connected to four voltage sources with different magnitudes,
- the gate of first SWS-FET is connected to the drain of second SWS-FET,
- the gate of second SWS-FET is connected to the drain of first SWS-FET,
- the gates of said two SWS-FETs connected to one end of channel of two access transistors,
- the said access transistors are conventional FETs,
- the other end of channel of conventional access FET is connected to Bitline and Bitline-Bar,
- the gates of said access transistors are connected to Wordline,
- said wordline access the stored bit depending on the voltage level applied to it.
A 2-bit Dynamic Access Memory (DRAM) cell comprising one Spatial Wavefunction Switched (SWS) FET and two storage capacitors,
- wherein said SWS-FETs comprise of at least two quantum well channels with appropriate barrier layers separating quantum wells, gate insulator layer, and gate contact layer, realized on appropriate substrate with buffer layers,
- said quantum well channels comprising of at least two sources and two drains,
- said drains are connected to one electrode of the two storage capacitors,
- the other plates or electrodes of said storage capacitors are connected to ground or appropriate voltage sources,
- said sources are connected to two Bit lines,
- said bit lines are used to Read and Write data stored in the capacitors,
- the gate of said SWS-FET is connected to the Word line,
- said Wordline access the stored bit depending on the voltage level applied to it.
Dependencies are inferred from the claim text.