3D semiconductor memory device and manufacturing method thereof
AssigneeInstitute of Microelectronics, Chinese Academy of Sciences
InventorsZongliang Huo, Ming Liu
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Abstract
The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.
Claims12
A 3D semiconductor memory device, comprising:
- a substrate, and
- a memory array consisting of one or more of memory cells located on the substrate, each string of memory cells comprising:
- a vertical-type gate-around transistor, and
- a vertical annular variable resistance unit, wherein
- in a bit line direction, the vertical-type gate-around transistors of the adjacent vertical strings of memory cells have a common source region, gates of the vertical-type gate-around transistors are isolated by an insulating layer, and upper electrodes of the vertical annular variable resistance units are isolated by the insulating layer, the common source region functioning as the bit line of the strings of memory cells;
- in a word line direction, the source regions of the vertical-type gate-around transistors of the adjacent vertical strings of memory cells are isolated by a shallow trench isolation, the gates of the vertical-type gate-around transistors are connected to each other, and the upper electrodes of the vertical annular variable resistance units are connected to each other;
- and
- the vertical annular variable resistance unit comprises one or more annular resistance sub-units arranged in a vertical direction, the annular resistance sub-units each comprising a variable resistance function layer having an annular shape, and the variable resistance function layers of adjacent annular resistance sub-units are isolated from each other by the insulating layer.
A method for manufacturing a 3D semiconductor memory device, comprising;
- forming a vertical-type gate-around transistor on a substrate;
- and
- forming a vertical annular variable resistance unit on the substrate on which the vertical-type gate-around transistor has been formed, so that manufacture of the 3D semiconductor memory device is completed, wherein the forming the vertical annular variable resistance unit comprises forming one or more annular resistance sub-units arranged in a vertical direction, the annular resistance sub-units each comprising a variable resistance function layer having an annular shape, and the variable resistance function layers of adjacent annular resistance sub-units are isolated from each other.
Dependencies are inferred from the claim text.