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US 8,999,848 B2Granted
Method for forming fine pattern of semiconductor device using double spacer patterning technology
AssigneeSK hynix Inc.
InventorsKi Lyoung Lee, Cheol Kyu Bok, Won Kyu Kim
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Abstract
A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.
Claims8
A method of forming a fine pattern of a semiconductor device, the method comprising:
- forming a second layer over a first layer;
- forming a partition pattern over the second layer;
- forming first spacers over sidewalls of the partition pattern;
- forming a first gap-fill layer filling between the first spacers;
- removing the first spacers;
- etching the second layer using the partition pattern and the first gap-fill layer as an etch mask to form a first pattern;
- forming second spacers over sidewalls of the first pattern;
- forming a second gap-fill layer filling between the second spacers;
- removing the second spacers;
- and
- etching the first layer using the first pattern and the second gap-fill layer as an etch mask to form a second pattern,
- wherein the first layer and the second gap-fill layer are formed of the same material.
9 more elements
Dependencies are inferred from the claim text.