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US 8,999,834 B2Granted
Sidewall-free CESL for enlarging ILD gap-fill window
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHan-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
Life of this patent
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Abstract
An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
Claims20
A method comprising:
- providing a first gate strip over a substrate and having a gate spacer on a sidewall of the first gate strip;
- forming a contact etch stop layer (CESL) over the gate strip and on a first sidewall of the gate spacer, a second sidewall of the gate spacer is opposite the first sidewall of the gate spacer and nearest the first gate strip, wherein a top portion of the CESL extends over the gate strip and a bottom portion of the CESL extends over the substrate, and wherein a sidewall portion of the CESL is disposed on the first sidewall of the gate spacer;
- etching the CESL and removing at least the sidewall portion of the CESL on the first sidewall of the gate spacer;
- and
- forming an inter-layer dielectric (ILD) over and contacting the CESL;
- wherein the CESL comprises a material having a high etch selectivity with respect to the ILD;
- wherein, after the etching, the bottom portion of the CESL is lower than a top surface of the gate spacer;
- wherein, after the etching, a top surface of the bottom portion of the CESL is higher than a bottom surface of the gate spacer;
- and
- wherein, after the etching, at least a portion of the first sidewall of the gate spacer is exposed through the CESL.
7 more elements
A method, comprising:
- providing a first conductive strip and a second conductive strip on a substrate;
- forming a first spacer on a first sidewall of the first conductive strip;
- forming a second spacer on a second sidewall of the second conductive strip, the first sidewall facing the second sidewall and the first spacer separated from the second spacer by a gap;
- forming a contact etch stop layer (CESL) over the first conductive strip and extending over the substrate in the gap, the CESL comprising a top portion directly over the first conductive strip, a bottom portion in the gap, and a sidewall portion disposed between the top portion and the bottom portion;
- modifying the CESL by removing the sidewall portion of the CESL such that the top portion and the bottom portion are separated, wherein the modifying the CESL comprises etching the CESL with an isotropic etch;
- and
- forming an inter-layer dielectric (ILD) over and contacting at least the bottom portion of the CESL.
4 more elements
A method, comprising:
- forming a first gate strip on a substrate;
- forming a gate spacer on a sidewall of the first gate strip, the gate spacer having a first sidewall opposite a second sidewall, the second sidewall of the gate spacer nearest the first gate strip;
- forming a contact etch stop layer (CESL) over the gate strip and extending over the first sidewall of the gate spacer and over the substrate adjacent to the gate strip;
- removing a sidewall CESL portion to expose at least a portion of the first sidewall of the gate spacer, the removing forming a top CESL portion separated from a bottom CESL portion;
- and
- forming an inter-layer dielectric (ILD) over and contacting the CESL;
- wherein, after removing the sidewall portion of the CESL, a top surface of the bottom CESL portion is higher than a bottom surface of the gate spacer.
4 more elements
Dependencies are inferred from the claim text.