Method and apparatus for controlling gate dimensions of memory devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Ming Wu, Shih-Chang Liu, Chia-Shiung Tsai
Life of this patent
Estimating the term…
Abstract
A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate spacer is over the memory gate electrode, a charge storage layer formed between the control gate structure and the memory gate structure, wherein the charge storage layer is an L-shaped structure, a first spacer along a sidewall of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
Claims20
A method comprising:
- forming a control gate structure over a substrate;
- depositing a charge storage layer over the control gate structure;
- depositing a memory gate layer over the charge storage layer, wherein the memory gate layer conforms to the charge storage layer;
- depositing a gate dimension controlling layer over the memory gate layer;
- applying an etch-back process to the memory gate layer;
- depositing a first dielectric layer over the memory gate layer;
- applying a first etching process to the first dielectric layer and the memory gate layer to form a first memory gate structure, wherein:
- the first memory gate structure is formed along a sidewall of the control gate structure;
- and
- the first memory gate comprises a memory gate and a remaining portion of the first dielectric layer;
- forming a first spacer along a sidewall of the first memory gate structure;
- applying a second etching process to the charge storage layer to form an L-shaped charge storage layer;
- and
- forming a second spacer over the memory gate structure.
A method comprising:
- forming a control gate structure over a substrate;
- forming an Oxide-Silicon-Oxide layer over the control gate structure;
- depositing a memory gate layer over the Oxide-Silicon-Oxide layer, wherein the memory gate layer is a conformal film;
- depositing a bottom anti-reflection coating layer over the memory gate layer, wherein the bottom anti-reflection coating layer partially fills an opening adjacent to the control gate structure;
- applying an etch-back process to the memory gate layer;
- depositing a memory gate spacer layer over the memory gate layer and the control gate structure;
- forming a first memory gate structure through a first etching process, wherein the first memory gate structure is formed along a sidewall of the control gate structure;
- forming a first spacer along a sidewall of the first memory gate structure;
- applying a second etching process to a silicon dot layer of the Oxide-Silicon-Oxide layer to form an L-shaped charge storage layer;
- and
- forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure.
A method comprising:
- depositing a charge storage layer over a control gate structure;
- depositing a memory gate layer over the charge storage layer;
- depositing a bottom anti-reflection coating layer, wherein the bottom anti-reflection coating layer is over a bottom portion of the memory gate layer and between two sidewall portions of the memory gate layer;
- applying an etch-back process to the memory gate layer;
- depositing a first dielectric layer over the memory gate layer;
- applying a first etching process to the first dielectric layer and the memory gate layer to form a first memory gate structure;
- forming a first spacer along a sidewall of the first memory gate structure;
- applying a second etching process to the charge storage layer to form an L-shaped charge storage layer;
- and
- forming a second spacer over the memory gate structure.
Dependencies are inferred from the claim text.