# US 8,999,828 B2 · Method and device for a split-gate flash memory with an extended word gate below a channel region

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- Number: US 8,999,828 B2
- Document ID: US8999828B2
- Status: Granted
- Kind: B2
- Application number: 13/197,367
- Filed: 2011-08-03
- Published: 2013-02-07
- Granted: 2015-04-07
- Earliest claimed: 2011-08-03
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: Eng Huat Toh; Shyue Seng (Jason) Tan
- Inventors: Eng Huat Toh; Shyue Seng (Jason) Tan
- Web page: https://patentgrep.com/patent/US8999828B2

## CPC

- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.

## Claims

### Claim 1

A method comprising:
providing a memory gate stack over a channel region;
providing a word gate extending from an upper portion at an upper surface of the memory gate stack to a lower portion below an upper surface of a substrate at the channel region and below an upper surface of the substrate at source and drain regions, wherein the lower portion of the word gate contacts both the channel region and a source or drain region, and wherein the upper portion of the word gate and the lower portion of the word gate have the same width; and
planarizing the memory gate stack and the word gate such that an upper surface of the memory gate stack and an upper surface of the word gate are substantially coplanar.

### Claim 2 (depends on 1)

The method according to claim 1, comprising:
forming a band engineered channel as the channel region.

### Claim 3 (depends on 2)

The method according to claim 2, further comprising:
forming the band engineered channel as a single layer or multiple layers.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising:
forming a buried channel in the substrate as the channel region.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising:
forming the buried channel 3 to 30 nm below the upper surface of the substrate.

### Claim 6 (depends on 1)

The method according to claim 1, comprising:
removing a portion of the memory gate stack to form an opening.

### Claim 7 (depends on 6)

The method according to claim 6, comprising:
forming a band engineered channel as the channel region;
forming the opening through the band engineered channel; and
providing a dielectric layer and the word gate in the opening.

### Claim 8 (depends on 6)

The method according to claim 6, comprising:
forming a buried channel as the channel region;
forming the opening alongside of and below the buried channel; and
providing a dielectric layer and the word gate in the opening.

### Claim 9 (depends on 1)

The method according to claim 1, comprising providing the word gate extending below the channel region.

### Claim 10 (depends on 1)

The method according to claim 1, further comprising:
providing the word gate extending at least 5 nanometers below the upper surface of the substrate.

### Claim 11

A method comprising:
providing a memory gate stack over a channel region;
removing a portion of the memory gate stack to form an opening;
providing a word gate, having sidewall spacers on side surfaces thereof and extending from an upper portion at an upper surface of the memory gate stack to a lower portion below an upper surface of a substrate at the channel region and below an upper surface of the substrate at source and drain regions, in the opening, wherein the lower portion of the word gate contacts both the channel region and a source or drain region, and wherein the upper portion of the word gate and the lower portion of the word gate have the same width; and
planarizing the memory gate stack and the word gate such that an upper surface of the memory gate stack and an upper surface of the word gate are substantially coplanar.

### Claim 12 (depends on 11)

The method according to claim 11, comprising:
providing a band engineered channel as the channel region; and
forming the opening such that it extends through the band engineered channel, wherein the word gate extends through the band engineered channel.

### Claim 13 (depends on 11)

The method according to claim 11, comprising:
providing a buried channel as the channel region; and
forming the opening such that it extends below the buried channel.