Semiconductor device with reduced gate length
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
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Abstract
A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.
Claims20
A semiconductor device comprising:
- a first type region comprising a first conductivity type;
- a second type region comprising a second conductivity type;
- a channel region extending between the first type region and the second type region;
- and
- a gate region surrounding the channel region, the gate region comprising a gate electrode, wherein a gate electrode length of the gate electrode is less than about 10 nm.
A method of forming a semiconductor device, the method comprising:
- forming a first type region comprising a first conductivity type;
- forming a second type region comprising a second conductivity type;
- forming a channel region extending between the first type region and the second type region;
- and
- forming a gate region surrounding the channel region, the gate region comprising a gate electrode, wherein a gate electrode length of the gate electrode is less than about 10 nm.
A method of forming a semiconductor device, the method comprising:
- forming a first type region comprising a first conductivity type;
- forming a second type region comprising a second conductivity type;
- forming a channel region extending between the first type region and the second type region;
- forming a first dielectric region on a first portion of the first type region;
- forming a gate electrode over the first dielectric region and surrounding the channel region, wherein a gate electrode length of the gate electrode is less than about 10 nm;
- and
- forming a second dielectric region on the gate electrode.
Dependencies are inferred from the claim text.