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US 8,999,798 B2Granted
Methods for forming NMOS EPI layers
AssigneeApplied Materials, Inc.
InventorsMitchell C. Taylor, Susan B. Felch
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AssigneeApplied Materials, Inc.
InventorsMitchell C. Taylor, Susan B. Felch
Estimating the term…
NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include (a) providing a substrate having a p-type silicon region; (b) depositing a silicon seed layer atop the p-type silicon region; (c) depositing a silicon-containing bulk layer comprising silicon, silicon and a lattice adjusting element or silicon and an n-type dopant atop the silicon seed layer; (d) implanting at least one of the lattice adjusting element or the n-type dopant which is absent from the silicon-containing bulk layer deposited in (c) into the silicon-containing bulk layer; and (e) annealing the silicon-containing bulk layer with an energy beam after implantation in (d). In some embodiments, the substrate may comprise a partially fabricated NMOS transistor device having a source/drain region defined therein.
A method for forming an n-type metal oxide semiconductor (NMOS) transistor, comprising:
A non-transitory computer readable medium having instructions stored thereon that, when executed by a processor, causes a semiconductor process tool to perform a method of forming an n-type metal oxide semiconductor (NMOS) transistor, comprising:
A method for forming an n-type metal oxide semiconductor (NMOS) transistor, comprising:
Dependencies are inferred from the claim text.