Asymmetrical replacement metal gate field effect transistor
AssigneeInternational Business Machines Corporation
InventorsVeeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh
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Abstract
An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region.
Claims13
A method for fabricating an asymmetrical field effect transistor (FET) device, the method comprising:
- forming a semiconductor structure having a substrate layer, a buried oxide (BOX) layer, a semiconductor-on-insulator (SOI) layer having a source and a drain region, a dummy gate on the SOI layer, and an offset spacer disposed around the dummy gate;
- removing at least a portion of the offset spacer and the dummy gate to expose a portion of the SOI layer;
- depositing a liner layer over the portion of the SOI layer and the offset spacer;
- implanting ions into a first portion of the liner layer;
- depositing an oxide film on a second portion of the liner layer;
- removing the first portion of the liner layer to form a trench between the oxide film and the offset spacer;
- forming an extended source region by implanting dopants in a portion of the SOI layer disposed beneath the trench;
- removing the oxide film and the second portion of the liner layer;
- depositing a high-k layer on exposed portions of the extended source region and the offset spacer;
- depositing a metal gate layer over the high-k layer;
- and
- forming a contact metal layer over the metal gate layer.
A method for fabricating an asymmetrical field effect transistor (FET) device, the method comprising:
- forming a semiconductor structure having a substrate layer, a buried oxide (BOX) layer, and a semiconductor-on-insulator (SOI) layer;
- forming a dummy gate on the SOI layer and an offset spacer disposed around the dummy gate;
- growing an epitaxial silicon region on one or more exposed portions of the SOI layer adjacent to the offset spacer;
- depositing a spacer layer on the epitaxial silicon regions and the offset spacer;
- removing a portion of the spacer layer disposed above the epitaxial silicon;
- forming a source and drain region in the SOI layer;
- depositing a nitride layer over the epitaxial silicon regions, the spacer layer and the offset spacer;
- removing portions of the dummy gate, the nitride layer, the spacer layer and the offset spacer to expose the dummy gate;
- removing the dummy gate;
- depositing a liner layer over an exposed portion of the SOI layer, the offset spacer, the spacer layer, and the nitride layer;
- implanting ions into a first portion of the liner layer;
- depositing an oxide film on a second portion of the liner layer that was not implanted with ions;
- forming a trench between the oxide film and the offset spacer by removing the first portion of the liner layer;
- forming an extended source region by implanting dopants in an area of the SOI layer beneath the trench;
- removing the oxide film and the second portion of the liner layer;
- depositing a high-k layer on exposed portions of the extend source region, the offset spacer, the spacer layer and the nitride layer;
- depositing a metal gate layer over the high-k layer;
- and
- forming a contact metal layer over the metal gate layer.
Dependencies are inferred from the claim text.