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US 8,999,794 B2Granted
Self-aligned source and drain structures and method of manufacturing same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsZiwei Fang, Ying Zhang, Jeff J. Xu
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Abstract
An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.
Claims22
A method comprising:
- forming a gate structure over a substrate, wherein the gate structure includes a gate electrode having a first sidewall surface and a gate dielectric having a second sidewall surface;
- forming a doped region in the substrate adjacent a channel region of the gate structure;
- performing a first etching process to remove the doped region and form a trench in the substrate, wherein the trench has a third sidewall surface that extends from the gate dielectric and is substantially coplanar with the first sidewall surface of the gate electrode and the second sidewall surface of the gate dielectric, wherein after performing the first etching process the trench is positioned closer to the channel region of the gate structure than any remaining portion of the doped region;
- and
- performing a second etching process that modifies the trench by removing portions of the substrate.
2 more elements
A method comprising:
- forming a gate structure over a semiconductor substrate;
- performing an implantation process to form a doped region in the semiconductor substrate, wherein the doped region is aligned with the gate structure, wherein the doped region has a cross-sectional profile shape;
- forming a spacer adjacent a sidewall of the gate structure, wherein the spacer is disposed over the doped region and has a bottommost surface facing the semiconductor substrate;
- performing a zero-biased plasma etching process that selectively etches the doped region from the substrate to form a trench, wherein the doped region is completely removed by performing the zero-biased plasma etching process, wherein the trench has the cross-sectional profile shape;
- modifying a profile of the trenches;
- and
- forming a source/drain feature in the trench having the modified profile, wherein the source/drain feature physically contacts the entire bottommost surface of the spacer.
4 more elements
A method comprising:
- forming a gate stack over a semiconductor substrate, wherein the gate stack interposes a first source/drain region and a second source/drain region, wherein the gate stack includes a gate electrode having a first sidewall surface and a gate dielectric having a second sidewall surface;
- forming an n-type doped region in the first source/drain region, wherein the n-type doped region is adjacent a channel region of the gate stack;
- performing a zero-biased plasma etching process that uses a chlorine-containing etching chemistry to selectively remove the n-type doped regions to form a trench in the first source/drain region, wherein after performing the zero-biased plasma etching process the trench is positioned closer to the channel region of the gate stack than any remaining portion of the doped region;
- and
- performing a biased etching process to modify a profile of the trench.
2 more elements
Dependencies are inferred from the claim text.