Formation of semiconductor structures with variable gate lengths

A method of forming a semiconductor structure comprising:

• providing a structure comprising a semiconductor substrate having a first active device region and a second active device region, and a sacrificial dielectric material located on a surface of the semiconductor substrate in the first active device region and the second active device region;
• forming a non-doped sacrificial semiconductor material portion having a first doped sacrificial semiconductor material portion of a first width located on each sidewall of said non-doped sacrificial semiconductor material portion on a portion of the sacrificial dielectric material and in the first active device region, and another non-doped sacrificial semiconductor material portion having a second doped sacrificial semiconductor material portion of a second width located on each sidewall of said another non-doped sacrificial semiconductor material portion on another portion of the sacrificial dielectric material and in the second active device region, wherein said second width is different than the first width, wherein said forming comprises:
• forming a first patterned sacrificial material stack in the first active device region, and a second patterned sacrificial material stack in the second active device region, wherein each of the first and second patterned material stacks includes at least a non-doped sacrificial semiconductor material layer portion;
• introducing a dopant within sidewalls of each non-doped sacrificial semiconductor material layer portion of the first patterned sacrificial material stack and the second patterned sacrificial material stack to form said non-doped sacrificial semiconductor material portion having the first doped sacrificial semiconductor material portion of the first width located on each sidewall of said non-doped sacrificial semiconductor material portion in each of said first and second active device regions;
• forming a block mask on said first active device region;
• widening the first doped sacrificial material portion within the second active device region to provide said another non-doped sacrificial semiconductor material portion having the second doped sacrificial semiconductor material portion of the second width within the second active device region;
• and
• removing the block mask;
• removing the non-doped sacrificial semiconductor material portion and the another non-doped sacrificial semiconductor material portion selective to each first doped sacrificial semiconductor material portion and each second doped sacrificial semiconductor material portion;
• removing exposed portions of the sacrificial dielectric material not covered by each first doped sacrificial semiconductor material portion in the first active device region and each second first doped sacrificial semiconductor material portion in the second active device region;
• forming at least a dielectric material adjacent each first doped sacrificial semiconductor material portion and each second doped sacrificial semiconductor material portion, wherein the dielectric material has an upper surface that is coplanar with an upper surface of each first doped sacrificial semiconductor material portion and each second doped sacrificial semiconductor material portion;
• removing each first doped sacrificial semiconductor material portion and underlying sacrificial dielectric material from the first active device region providing first gate cavities having said first width, and each second doped sacrificial semiconductor material portion and underlying sacrificial dielectric material from the second active device region providing second gate cavities having said second width;
• and
• forming a gate structure in each of said first gate cavities and said second gate cavities.