Reducing source contact to gate spacing to decrease transistor pitch

A method of forming a transistor, the method comprising:

• forming a gate over an active area of the transistor;
• forming a lightly doped drain (LDD) in a drain region of the transistor using a first mask blocking a source region of the transistor, the LDD having a first doping profile;
• forming a source extension in the source region of the transistor using a second mask blocking the drain region of the transistor, the source extension having a second doping profile deeper than the first doping profile;
• forming a source and a drain aligned to the gate in the active area;
• and
• forming a source contact and a drain contact respectively over the source and the drain, wherein a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor.