Integration of high voltage trench transistor with low voltage CMOS transistor

A method of forming a semiconductor device comprising:

• providing a substrate defined with a device region, wherein the device region comprises a first polarity type first doped well;
• forming a gate having an upper and a lower portion in a trench in the substrate, the upper portion forms a gate electrode and the lower portion forms a gate field plate, wherein an inner edge of the gate field plate is offset from an inner edge of the gate electrode;
• forming second and third doped wells disposed within the first doped well, wherein
• the second doped well comprises first polarity type dopants and the third doped well comprises second polarity type dopants,
• the second doped well comprises a dopant concentration different to the first doped well, and
• the third doped well comprises a depth shallower than the gate electrode;
• forming first and second surface doped regions adjacent to the gate;
• and
• wherein the gate field plate introduces a vertical reduced surface (RESURF) effect in a drift region of the device.

A semiconductor device comprising:

• a substrate comprising a first polarity type first doped well;
• a gate having an upper and a lower portion in a trench in the substrate, wherein the upper portion forms a gate electrode and the lower portion forms a gate field plate;
• second and third doped wells disposed within the first doped well, wherein
• the second doped well comprises first polarity type dopants and the third doped well comprises second polarity type dopants,
• the second doped well comprises a dopant concentration different to the first doped well, and
• the third doped well comprises a depth shallower than the gate electrode;
• first and second surface doped regions adjacent to the gate;
• and
• wherein the gate field plate introduces a vertical reduced surface (RESURF) effect in a drift region of the device.